search for: d8705

...rite by Jonas Paulsson (cc'd). If you can't find the discussions > on the mailing list, please let us know. > > -Hal > > > > Thanks for the response. > > > Do you mean "ScheduleDAGInstrs::buildSchedGraph() rewritten" > http://reviews.llvm.org/D8705 ? If yes it is not the same fragment > of code. Ah, I see. That bug deals with ScheduleDAGRRList. Andy, I thought that with the transition to source-order SDAG scheduling (and using MI scheduling instead), we were going to essentially get rid of that code. Is that right? -Hal > > &g...

Hi, (This only concerns MISNeedChainEdge(), and is separate from D8705) I found out that the MIScheduler (pre-ra) could not handle a simple test case (test/CodeGen/SystemZ/alias-01.ll), with 16 independent load / add / stores. The buildSchedGraph() put too many edges between memory accesses, because 1) There was no implementation of areMemAccessesTriviallyDisjoint...

----- Original Message ----- > From: "Paweł Bylica" <chfast at gmail.com> > To: "LLVMdev" <llvmdev at cs.uiuc.edu> > Sent: Friday, May 22, 2015 8:45:11 AM > Subject: Re: [LLVMdev] Problems with instruction scheduling > > > > Any comments? Not in particular, but I think we're pretty close to applying a rewrite by Jonas Paulsson

Hello, While tuning the MIScheduler for my target, I discovered a code that unnecessarily restricts the scheduler. I think this is a bug, but I would appreciate a second opinion. In file ScheduleDAGInstrs.cpp, the function MIsNeedChainEdge determines whether two MachineInstrs are ordered by a memory dependence. It first runs through the standard criteria (Do both instructions access memory?