Displaying 2 results from an estimated 2 matches for "d86175c1".
2015 Apr 11
2
[LLVMdev] How doesn't llvm generate IR for logical negate operation
Yes, but my point is that there would be some overhead to do cast the <N x
i1> vectortype to an integerNty. Is there any good way to check not all of
these N bits in the vectortype are 0s?
On Fri, Apr 10, 2015 at 5:37 PM, Bruce Hoult <bruce at hoult.org> wrote:
> Sure, if you actually just want an i1 saying whether or not at least one
> bit is set to 1, then comparing against 0
2015 Apr 11
2
[LLVMdev] How doesn't llvm generate IR for logical negate operation
...s and
>> dangerous content by *MailScanner* <http://www.mailscanner.info/>, and
>> is
>> believed to be clean.
>>
>
>
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