search for: d7bd4b06

Displaying 3 results from an estimated 3 matches for "d7bd4b06".

2010 Sep 07
0
[LLVMdev] Complex regalloc contraints
On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote: > The machine I am targeting has some special requirements for some > operations, say: > > ADD or1, ir1, r5 > > would add ir1 (input reg 1) and r5 and put the result in or1 (output reg > 1). The point id that input and output regs have to go paired (this > meaning an addition of ir1 with whatever always goes to
2010 Sep 07
2
[LLVMdev] Complex regalloc contraints
Hi all, The machine I am targeting has some special requirements for some operations, say: ADD or1, ir1, r5 would add ir1 (input reg 1) and r5 and put the result in or1 (output reg 1). The point id that input and output regs have to go paired (this meaning an addition of ir1 with whatever always goes to or1, or an in general irX + whatever goes to orX). AFAIK, InstrInfo.td only allow
2010 Sep 08
3
[LLVMdev] Complex regalloc contraints
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