search for: d71387

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2020 Jan 06
2
Encode target-abi into LLVM bitcode for LTO.
...codegen so the problem is how to pass ABI info >> into LTO code generator. >> >> The easier way is pass -target-abi via option to LTO codegen, but there >> is linking issue when linking two bitcodes generated by different -mabi >> option. (see https://reviews.llvm.org/D71387#1792169) >> >> Usually the ABI info for a file is derived from target triple, mcpu or >> -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr >> option, so the one of solutions is encoding target-abi in IR via LLVM >> module flags metadata. >> &...
2020 Jan 06
2
Encode target-abi into LLVM bitcode for LTO.
Hi all. There are two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169) Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr option, so the one of solutions is encoding target-abi in IR via LLVM module flags metadata. But there is an another issue in assembler. In curren...
2020 Jan 07
2
Encode target-abi into LLVM bitcode for LTO.
...> There are two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. > > The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169 <https://reviews.llvm.org/D71387#1792169>) > > Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr option, so the one of solutions is encoding target-abi in IR via LLVM module flags metada...
2020 Jan 07
2
Encode target-abi into LLVM bitcode for LTO.
...here are two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. >> >> The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169 <https://reviews.llvm.org/D71387#1792169>) >> >> Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr option, so the one of solutions is encoding target-abi in IR via LLVM module flag...
2020 Jan 08
3
Encode target-abi into LLVM bitcode for LTO.
...O code generator. >>>>>> >>>>>> The easier way is pass -target-abi via option to LTO codegen, but >>>>>> there is linking issue when linking two bitcodes generated by different >>>>>> -mabi option. (see https://reviews.llvm.org/D71387#1792169) >>>>>> >>>>>> Usually the ABI info for a file is derived from target triple, mcpu >>>>>> or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr >>>>>> option, so the one of solutions is encoding targ...
2020 Jan 09
2
Encode target-abi into LLVM bitcode for LTO.
...t;>>>> >>>>>>>> The easier way is pass -target-abi via option to LTO codegen, but >>>>>>>> there is linking issue when linking two bitcodes generated by different >>>>>>>> -mabi option. (see https://reviews.llvm.org/D71387#1792169) >>>>>>>> >>>>>>>> Usually the ABI info for a file is derived from target triple, mcpu >>>>>>>> or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr >>>>>>>> option, so the o...
2020 Jan 10
2
Encode target-abi into LLVM bitcode for LTO.
...two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. >>> >>> The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169) >>> >>> Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr option, so the one of solutions is encoding target-abi in IR via LLVM module flags metadata. >>> >>> B...
2020 Jan 13
2
Encode target-abi into LLVM bitcode for LTO.
...how to pass ABI >> info into LTO code generator. >> >>> >> >>> The easier way is pass -target-abi via option to LTO codegen, but >> there is linking issue when linking two bitcodes generated by different >> -mabi option. (see https://reviews.llvm.org/D71387#1792169) >> >>> >> >>> Usually the ABI info for a file is derived from target triple, mcpu >> or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr >> option, so the one of solutions is encoding target-abi in IR via LLVM >> module...
2020 Jan 15
2
Encode target-abi into LLVM bitcode for LTO.
...nto LTO code generator. >>>> >>> >>>> >>> The easier way is pass -target-abi via option to LTO codegen, but >>>> there is linking issue when linking two bitcodes generated by different >>>> -mabi option. (see https://reviews.llvm.org/D71387#1792169) >>>> >>> >>>> >>> Usually the ABI info for a file is derived from target triple, mcpu >>>> or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr >>>> option, so the one of solutions is encoding target-abi...
2020 Jan 27
2
Encode target-abi into LLVM bitcode for LTO.
...problem is how to pass ABI > info into LTO code generator. > > >>> > > >>> The easier way is pass -target-abi via option to LTO codegen, but > there is linking issue when linking two bitcodes generated by different > -mabi option. (see https://reviews.llvm.org/D71387#1792169) > > >>> > > >>> Usually the ABI info for a file is derived from target triple, mcpu > or -mabi, but in RISC-V, target-abi is only derived from -mabi and -mattr > option, so the one of solutions is encoding target-abi in IR via LLVM > module flags meta...
2020 Jan 27
2
Encode target-abi into LLVM bitcode for LTO.
...info into LTO code generator. >>> > >>> >>> > >>> The easier way is pass -target-abi via option to LTO codegen, but >>> there is linking issue when linking two bitcodes generated by different >>> -mabi option. (see https://reviews.llvm.org/D71387#1792169) >>> > >>> >>> > >>> Usually the ABI info for a file is derived from target triple, >>> mcpu or -mabi, but in RISC-V, target-abi is only derived from -mabi and >>> -mattr option, so the one of solutions is encoding target-abi in IR...