search for: d61879

...rsp) at line 7 can be > > removed because of the store at line 35. > > These are in different basic blocks. IIRC there are a bunch of cases where DCE just fails when there’s any control flow. I think this is what you’re seeing here. I think Vitaly's patches (https://reviews.llvm.org/D61879) should allow DSE to work across basic blocks. But, as you mentioned, the problem is that we only have a memset at IR level. > > > Same for store to 24(%rsp), which is later overwritten at lines 11 and 16. > > I’m not sure what we should do here… If it were a constant store we’d fold...

...the store at line 35. >> > > >> > These are in different basic blocks. IIRC there are a bunch of cases >> where DCE just fails when there’s any control flow. I think this is what >> you’re seeing here. >> I think Vitaly's patches (https://reviews.llvm.org/D61879) should >> allow DSE to work across basic blocks. But, as you mentioned, the >> problem is that we only have a memset at IR level. >> > >> > > Same for store to 24(%rsp), which is later overwritten at lines 11 >> and 16. >> > >> > I’m not sur...

..., !dbg !27 call void @llvm.memset.p0i8.i64(i8* nonnull align 8 %0, i8 0, i64 40, i1 false), !dbg !28 Clang only splits memsets into series of stores under certain conditions, so it's hard to remove redundant stores on the IR level (even with the recent DSE patches: https://reviews.llvm.org/D61879). In the resulting assembly, however, the memset is lowered into a series of MOVQ instructions (see the attached ipt.s file), of which at least the stores to 24(%rsp) and 16(%rsp) are redundant. Given that at MCInst level we already know if a memset is split into a sequence of stores, can we do a...

...* nonnull align 8 %0, i8 0, i64 > > 40, i1 false), !dbg !28 > > > > Clang only splits memsets into series of stores under certain > > conditions, so it's hard to remove redundant stores on the IR level > > (even with the recent DSE patches: https://reviews.llvm.org/D61879). > > In the resulting assembly, however, the memset is lowered into a > > series of MOVQ instructions (see the attached ipt.s file), of which at > > least the stores to 24(%rsp) and 16(%rsp) are redundant. > > > > Given that at MCInst level we already know if a memset...

> On May 10, 2019, at 8:59 PM, Vitaly Buka via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Sorry for delay, I was busy with other stuff. > CTMark results. > > dse is the current DSE. > dsem is my experimental module level DSE. > dsem runs after dse, so it's additionally deleted stores. > > -O3 > dse - Number of stores deleted