Displaying 3 results from an estimated 3 matches for "d60052".
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d60012
2019 Apr 28
2
[GSoC] Supporting Efficiently the Shift-vector Instructions of the Connex Vector Processor
...memory accesses in LLVM - this seems to be already well supported in GCC.
Please note also our Connex vector processor back end has been reviewed and we should
be accepted as experimental (also because it has a few "exotic" features) - see, if
interested, https://reviews.llvm.org/D60052 .
Best regards,
Alex
On 4/9/2019 1:38 PM, Anton Korobeynikov via llvm-dev wrote:
> Hello Andrei,
>
> You proposal seems to be centered on improvements of out-of-tree
> backend entirely and therefore is not entirely clear what are the
> benefits of this project to the LLVM...
2019 Apr 08
2
[GSoC] Supporting Efficiently the Shift-vector Instructions of the Connex Vector Processor
Hello,
I am applying for Google Summer of Code with a project related to LLVM and Connex SIMD processor and I would appreciate some feedback on the proposal.
The proposal can be found here:
https://docs.google.com/document/d/1pBRbW8pU9GV8zWCJQrILhynNEBpGXJKtev1j7ekXfqs/edit?usp=sharing
Thank you,
Andrei Popa
2018 Apr 04
2
LLVM back end for the research Connex SIMD processor
Hello.
I'd like to advertise the LLVM back end I developed in the last 2 years for the
research Connex wide SIMD processor, which can have up to 4096 lanes. The Connex SIMD
processor is designed to run efficiently BLAS routins, is an easily reconfigurable
low-power processor with scratchpad memory, a shift register for inter-lane communication,
a hardware sum-reduction tree and