search for: d5_d6

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2013 Apr 19
0
[LLVMdev] MachineOperand SubReg
...you can see, D1 has two super-registers, neither is more super than the other. We similarly define triples and quads of consecutive D-registers. NEON also has 128-bit vector instructions operating on even-odd pairs of D-registers, so the actual register names we use are: Q0, D1_D2, Q1, D3_D4, Q2, D5_D6, ... Here, Q0 is the name we use for D0_D1 (which doesn't exist). This register structure also means that the complete set of aliasing registers can get quite large. Some NEON registers have more than 40 aliases. The register units help control that complexity. Each physreg has an associated s...
2013 Apr 19
2
[LLVMdev] MachineOperand SubReg
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> A MachineOperand has both a getReg() and a getSubReg() interface. >> For a physical register operand, is getReg() guaranteed to be the >> "most super" register with getSubReg() providing the specific >> subregister information for the operand? If so then for my current >> purposes it seems I