Displaying 4 results from an estimated 4 matches for "d54d3a6a871e5127a6ed".
2015 Oct 30
2
Vectorizing structure reads, writes, etc on X86-64 AVX
...ing on LLVM, but I do know a bit about
compilation generally.
I am on x86-64 and I am interested in structure reads, writes, and
constants being optimized to use vector registers when the alignment
and sizes are right. I have created a gist of a small example:
https://gist.github.com/jeapostrophe/d54d3a6a871e5127a6ed
The assembly is produced with
llc -O3 -march=x86-64 -mcpu=corei7-avx
The key idea is that we have a structure like this:
%athing = type { float, float, float, float, float, float, i16, i16,
i8, i8, i8, i8 }
That works out to be 32 bytes, so it can fit in YMM registers.
If I have two pointers...
2015 Nov 03
2
Vectorizing structure reads, writes, etc on X86-64 AVX
...enerally.
>>
>> I am on x86-64 and I am interested in structure reads, writes, and
>> constants being optimized to use vector registers when the alignment
>> and sizes are right. I have created a gist of a small example:
>>
>> https://gist.github.com/jeapostrophe/d54d3a6a871e5127a6ed
>>
>> The assembly is produced with
>>
>> llc -O3 -march=x86-64 -mcpu=corei7-avx
>>
>> The key idea is that we have a structure like this:
>>
>> %athing = type { float, float, float, float, float, float, i16, i16,
>> i8, i8, i8, i8 }
>>
&g...
2015 Nov 03
2
Vectorizing structure reads, writes, etc on X86-64 AVX
...x86-64 and I am interested in structure reads, writes, and
> >> constants being optimized to use vector registers when the
> >> alignment
> >> and sizes are right. I have created a gist of a small example:
> >>
> >> https://gist.github.com/jeapostrophe/d54d3a6a871e5127a6ed
> >>
> >> The assembly is produced with
> >>
> >> llc -O3 -march=x86-64 -mcpu=corei7-avx
> >>
> >> The key idea is that we have a structure like this:
> >>
> >> %athing = type { float, float, float, float, float, float, i16...
2015 Nov 04
2
Vectorizing structure reads, writes, etc on X86-64 AVX
...ds, writes, and
> >> >> constants being optimized to use vector registers when the
> >> >> alignment
> >> >> and sizes are right. I have created a gist of a small example:
> >> >>
> >> >> https://gist.github.com/jeapostrophe/d54d3a6a871e5127a6ed
> >> >>
> >> >> The assembly is produced with
> >> >>
> >> >> llc -O3 -march=x86-64 -mcpu=corei7-avx
> >> >>
> >> >> The key idea is that we have a structure like this:
> >> >>
> >> >...