search for: d480

Hello, I''m currently trying to understand some problems I had in the past with mixing look-back with blktap(2) for HV and PV domains. I''m stuck reading the source code, so I''d like to get some help from the list. Interrupt me if I got something fundamentally wrong in my understanding so far: 1. With pure-HV the domU gets an emulated IDE (or whatever) disk. The

...Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 74 Region 0: I/O ports at d880 [size=8] Region 1: I/O ports at d800 [size=4] Region 2: I/O ports at d480 [size=8] Region 3: I/O ports at d400 [size=4] Region 4: I/O ports at d080 [size=32] Region 5: Memory at faffc000 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] MSI: Enable+ Count=1/16 Maskable- 64bit- Address: fee00000 Data: 404a Capabilities: [70] Power Management version 3 Flag...

...HyperTransport: MSI Mapping > > 00:09.0 IDE interface: nVidia Corporation MCP67 AHCI Controller (rev a2) (prog-if 85 [Master SecO PriO]) > Subsystem: ASUSTeK Computer Inc. Unknown device 82b3 > Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 233 > I/O ports at d480 [size=8] > I/O ports at d400 [size=4] > I/O ports at d080 [size=8] > I/O ports at d000 [size=4] > I/O ports at cc00 [size=16] > Memory at feafa000 (32-bit, non-prefetchable) [size=8K] > Capabilities: [44] Power Management version 2 &...

...ilities: [8c] HyperTransport: MSI Mapping > > 00:09.0 IDE interface: nVidia Corporation MCP67 AHCI Controller (rev a2) (prog-if 85 [Master SecO PriO]) > Subsystem: ASUSTeK Computer Inc. Unknown device 82b3 > Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 233 > I/O ports at d480 [size=8] > I/O ports at d400 [size=4] > I/O ports at d080 [size=8] > I/O ports at d000 [size=4] > I/O ports at cc00 [size=16] > Memory at feafa000 (32-bit, non-prefetchable) [size=8K] > Capabilities: [44] Power Management version 2 > Capabilities: [8c] #12 [0010] > &...

...pchp 09:00.0 SATA controller: Device 1b4b:9123 (rev 10) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. Device 8400 Flags: bus master, fast devsel, latency 0, IRQ 55 I/O ports at dc00 [size=8] I/O ports at d880 [size=4] I/O ports at d800 [size=8] I/O ports at d480 [size=4] I/O ports at d400 [size=16] Memory at f7dff000 (32-bit, non-prefetchable) [size=2K] Expansion ROM at f7de0000 [disabled] [size=64K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit- Capabilities: [70] Expr...

Hey hope this opne is a "make senser". Has anyone tried the "Subject line" combo?, I''ve compiled a dozen src.rpm kernel 3.0 and 3.1 packages with no luck to try native upstream Dom0 kernel support with no success, just a kernel oops and constant reboots. I followed Fedora''s wiki on building a custom kernel, even used F16''s .config which also was a

Hey hope this opne is a "make senser". Has anyone tried the "Subject line" combo?, I''ve compiled a dozen src.rpm kernel 3.0 and 3.1 packages with no luck to try native upstream Dom0 kernel support with no success, just a kernel oops and constant reboots. I followed Fedora''s wiki on building a custom kernel, even used F16''s .config which also was a

Now that x86-64 has directly accessible percpu variables, it can also implement the direct versions of these operations, which operate on a vcpu_info structure directly embedded in the percpu area. In fact, the 64-bit versions are more or less identical, and so can be shared. The only two differences are: 1. xen_restore_fl_direct takes its argument in eax on 32-bit, and rdi on 64-bit.