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I'm working with Andrew on D43515 right now, and some of these unanswered questions are directly relevant to that patch. So.... On Fri, Feb 09, 2018 at 03:42:20PM +0100, Ulrich Weigand wrote: > C) Floating-point exceptions > If a mask bit in the floating-point status register is set, then all FP > instructions wi...

...orm > and floating-point operation into a constrained intrinsic > if *any* (other) module already uses the latter. > > - At the IR level, complete the set of supported constrained > FP intrinsics (there are still some missing, see e.g > https://reviews.llvm.org/D43515 <https://reviews.llvm.org/D43515>). > Also, it seems not all variants (e.g. for vector types) are > supported correctly through codegen (see e.g. > https://reviews.llvm.org/D46967 <https://reviews.llvm.org/D46967>). > > - Allow targets to correctly reflect...

...automatically transform > and floating-point operation into a constrained intrinsic > if *any* (other) module already uses the latter. > > - At the IR level, complete the set of supported constrained > FP intrinsics (there are still some missing, see e.g > https://reviews.llvm.org/D43515). > Also, it seems not all variants (e.g. for vector types) are > supported correctly through codegen (see e.g. > https://reviews.llvm.org/D46967). > > - Allow targets to correctly reflect constrained intrinsics > semantics at the MI level and final machine code generation > (s...

...e, have the LTO pass automatically transform and floating-point operation into a constrained intrinsic if *any* (other) module already uses the latter. - At the IR level, complete the set of supported constrained FP intrinsics (there are still some missing, see e.g https://reviews.llvm.org/D43515). Also, it seems not all variants (e.g. for vector types) are supported correctly through codegen (see e.g. https://reviews.llvm.org/D46967). - Allow targets to correctly reflect constrained intrinsics semantics at the MI level and final machine code generation (see e.g. https://reviews....

...>> and floating-point operation into a constrained intrinsic >> if *any* (other) module already uses the latter. >> >> - At the IR level, complete the set of supported constrained >> FP intrinsics (there are still some missing, see e.g >> https://reviews.llvm.org/D43515). >> Also, it seems not all variants (e.g. for vector types) are >> supported correctly through codegen (see e.g. >> https://reviews.llvm.org/D46967). >> >> - Allow targets to correctly reflect constrained intrinsics >> semantics at the MI level and final machine...

I think we're going to need to create a new mechanism to communicate strict FP modes to the backend. I think we need to avoid doing anything that will require re-inventing or duplicating all of the pattern matching that goes on in instruction selection (which is the reason we're currently dropping that information). I'm out of my depth on this transition, but I think maybe we could