Displaying 7 results from an estimated 7 matches for "d3test".
2018 Aug 28
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...For Linux, I only see one write at startup, none on runtime resume.
I did not test system sleep/resume. (disable/enable is arguably a bit
different from system s/r, you may want to do additional testing here.)
Full log for WIndows 10 and Linux:
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/slogs/win10-rp-enable-disable.txt#L3418
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/slogs/linux-rp.txt
lspci for the emulated bridge:
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/XPS9560/lspci-vm-vfio.txt#L359
The rp_*_config trace points are non-stand...
2018 Aug 28
6
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
On Fri, Aug 24, 2018 at 11:42 PM, Peter Wu <peter at lekensteyn.nl> wrote:
> Are these systems also affected through runtime power management? For
> example:
>
> modprobe nouveau # should enable runtime PM
> sleep 6 # wait for runtime suspend to kick in
> lspci -s1: # runtime resume by reading PCI config space
>
> On laptops from
2018 Aug 30
2
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
On Tue, Aug 28, 2018 at 5:57 PM, Peter Wu <peter at lekensteyn.nl> wrote:
> Just to be sure, after "sleep", do both devices report "suspended" in
> /sys/bus/pci/devices/0000:00:1c.0/power/runtime_status
> /sys/bus/pci/devices/0000:01:00.0/power/runtime_status
>
> and was this reproduced with a recent mainline kernel with no special
> cmdline options? The
2018 Sep 05
1
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
On Tue, Aug 28, 2018 at 5:57 PM, Peter Wu <peter at lekensteyn.nl> wrote:
> Only non-bridge devices can be passed to a guest, but perhaps logging
> access to the emulated bridge is already sufficient. The Prefetchable
> Base Upper 32 Bits register is at offset 0x28.
>
> In a trace where the Nvidia device is disabled/enabled via Device
> Manager, I see writes on the enable
2018 Aug 30
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...ot; method that emulates at least
the "Optimus" interface for GUID a486d8f8-0bda-471b-a72b-6042a6b5bee0.
You probably lost interest here, but if you want to continue anyway this
is what allowed me to install the driver on the XPS 9560:
https://github.com/Lekensteyn/acpi-stuff/blob/master/d3test/fakedev.asl
If you adapt if for your environment, note:
- I have only tested this with the q35 machine type with an additional
ioh3420 root port. See the XPS956/boot-vm script.
- The \_SB.PCI0.SE0 device should match the root port:
cat /sys/bus/pci/devices/0000:00:1c.0/firmware_node/path
(th...
2018 Aug 24
0
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
...ike disabling MSI/interrupts before
suspend, setting the Enable Clock Power Management bit in PCI Express
Link Control and more, but applying these changes were so far not really
successful.
Some supporting files for that investigation are here:
https://github.com/Lekensteyn/acpi-stuff/tree/master/d3test
Karol noticed that by not setting the State in PMCSR to D3 for the
Nvidia GPU during runtime suspend, then the device would successfully
resume. However, based on traces using VFIO-PCI, it does not seem a good
solution as Windows does not behave like that.
--
Kind regards,
Peter Wu
https://lekens...
2018 Aug 24
2
Rewriting Intel PCI bridge prefetch base address bits solves nvidia graphics issues
Hi,
We are facing a suspend/resume problem with many different Asus laptop
models (30+ products) with Intel chipsets (multiple generations) and
nvidia GPUs (several different ones). Reproducers include:
1. Boot
2. Suspend/resume
3. Load nouveau driver
4. Start X
5. Observe slow X startup and many many errors in logs (primarily
nouveau fifo faults)
or
1. Boot
2. Load nouveau driver
3. Start X