search for: d3_d4

...d1, d2}, [r0] The instruction loads two d-registers, but they must be consecutive. ARM also names even-odd pairs of d-registers, q0 = {d0, d1}, but odd-even pairs have no other name than {d1, d2}. LLVM models the sequence constraint as a single super-register, so we define pseudo-registers D1_D2, D3_D4, … in addition to the existing Q0, Q1, … From the register allocator's point of view, the vld1.64 instruction has two operands: a GPR operands for the address, and a DPair operand representing the two consecutive d-registers. This model makes it easy to handle register sequence constraints, an...

...isters. As you can see, D1 has two super-registers, neither is more super than the other. We similarly define triples and quads of consecutive D-registers. NEON also has 128-bit vector instructions operating on even-odd pairs of D-registers, so the actual register names we use are: Q0, D1_D2, Q1, D3_D4, Q2, D5_D6, ... Here, Q0 is the name we use for D0_D1 (which doesn't exist). This register structure also means that the complete set of aliasing registers can get quite large. Some NEON registers have more than 40 aliases. The register units help control that complexity. Each physreg has an a...

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> A MachineOperand has both a getReg() and a getSubReg() interface. >> For a physical register operand, is getReg() guaranteed to be the >> "most super" register with getSubReg() providing the specific >> subregister information for the operand? If so then for my current >> purposes it seems I