Displaying 5 results from an estimated 5 matches for "d39400".
2017 Oct 31
2
Reaching definitions on Machine IR post register allocation
...that wants to rename registers after
RA (unless the renaming is done right after RA when virtual registers
are still present, which is what my current patch does, and is the
source of complexity that I'm trying to eliminate).
[1] https://reviews.llvm.org/D30751
[2] https://reviews.llvm.org/D39400 D39400 WIP: [MachineOperand][MIR]
Add isRenamable to MachineOperand.
On 10/31/2017 5:49 AM, Raghavan, Venugopal via llvm-dev wrote:
> Hi Krzysztof,
>
> Thanks a lot for taking the time to write a detailed explanation. I
> think I understand things better now.
>
> I am trying...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
...ass that wants to rename registers after RA (unless the renaming is done right after RA when virtual registers are still present, which is what my current patch does, and is the source of complexity that I'm trying to eliminate).
[1] https://reviews.llvm.org/D30751
[2] https://reviews.llvm.org/D39400 D39400 WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand.
On 10/31/2017 5:49 AM, Raghavan, Venugopal via llvm-dev wrote:
> Hi Krzysztof,
>
> Thanks a lot for taking the time to write a detailed explanation. I
> think I understand things better now.
>
> I am trying...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
...fter RA when virtual registers are still present, which
>>> is what my current patch does, and is the source of complexity that
>>> I'm trying to eliminate).
>>>
>>> [1] https://reviews.llvm.org/D30751
>>> [2] https://reviews.llvm.org/D39400 D39400 WIP:
>>> [MachineOperand][MIR] Add isRenamable to MachineOperand.
>>>
>>> On 10/31/2017 5:49 AM, Raghavan, Venugopal via llvm-dev wrote:
>>>
>>> Hi Krzysztof,
>>>
>>> Thanks a lot for taking the time to wr...
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...s the renaming is
> done right after RA when virtual registers are still present, which
> is what my current patch does, and is the source of complexity that
> I'm trying to eliminate).
>
> [1] https://reviews.llvm.org/D30751
> [2] https://reviews.llvm.org/D39400 D39400 WIP:
> [MachineOperand][MIR] Add isRenamable to MachineOperand.
>
> On 10/31/2017 5:49 AM, Raghavan, Venugopal via llvm-dev wrote:
>
> Hi Krzysztof,
>
> Thanks a lot for taking the time to write a detailed explanation. I
> think I un...
2017 Sep 12
6
Reaching definitions on Machine IR post register allocation
Hi Venu,
> On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi Krzysztof,
>
> Thanks for your reply.
>
> I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this?
No concrete plan, no. We've been thinking about for quite some time now, but