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I would like to revive this thread, as I am struggling a lot with the FP16 implementation in the ARM backend. My implementation in https://reviews.llvm.org/D38315 is finished (except one case), but a more robust alternative implementation was suggested. One can indeed argue that my current implementation is a bit fragile, because it involves manually patching up the isel dags for a few cases. The suggestion was to look into CCState and adjusting of the calli...

Thanks a lot for the suggestions! I will look into using vld1/vst1, sounds good. I am custom lowering the bitcasts, that's now the only place where FP_TO_FP16 and FP16_TO_FP nodes are created to avoid inefficient code generation. I will double check if I can't achieve the same without using these nodes (because I really would like to get completely rid of them). Cheers, Sjoerd.

...ijer; Sam Parker; Oliver Stannard; llvm-dev at lists.llvm.org Cc: nd Subject: Re: [llvm-dev] [RFC] Half-Precision Support in the Arm Backends I would like to revive this thread, as I am struggling a lot with the FP16 implementation in the ARM backend. My implementation in https://reviews.llvm.org/D38315 is finished (except one case), but a more robust alternative implementation was suggested. One can indeed argue that my current implementation is a bit fragile, because it involves manually patching up the isel dags for a few cases. The suggestion was to look into CCState and adjusting of the calli...

...ng in integer registers, hard float, hard float with FP16, and hard float with FullFP16, that makes things interesting. My AArch32 implementation in the ARM backend is nearly complete and I am working on fixing a handful of regression tests (the WIP diff can be found here: https://reviews.llvm.org/D38315). My approach to handle f16 types should not lead to any codegen differences for existing tests, but the way half types are handled and legalized is totally different in some cases and from that point of view the changes could be considered intrusive. Thus, this is a heads up, and below I will disc...