Displaying 1 result from an estimated 1 matches for "d35ceca3".
2015 Nov 11
2
[AArch64] Address computation folding
Hi,
Indeed, the complex add is more expensive on all Cortex cores I know of.
However there is an important point here that the code sequence we generate
requires two registers live instead of one. In high regpressure loops, were
probably losing performance.
James
On Wed, 11 Nov 2015 at 21:09, Tim Northover via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 11 November 2015 at