search for: d23561

...l slot size or alignment. > > Since the number of targets allowing this kind of variability is growing (besides Hexagon, there is RISC-V, MIPS, and out of tree targets, such as CHERI), LLVM should allow convenient handling of this type of a situation. See comments in https://reviews.llvm.org/D23561 <https://reviews.llvm.org/D23561>for more details. > > ARM SVE sounds like it will have similar issues: https://community.arm.com/groups/processors/blog/2016/08/22/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture <https://community.arm.com/groups/proc...

...al spill slot size or alignment. Since the number of targets allowing this kind of variability is growing (besides Hexagon, there is RISC-V, MIPS, and out of tree targets, such as CHERI), LLVM should allow convenient handling of this type of a situation. See comments in https://reviews.llvm.org/D23561 for more details. General approach: 1. Introduce a concept of a hardware "mode". This "mode" should be immutable, that is, it should be treated as a fixed property of the hardware throughout the execution of the program being compiled. This is different from, for example,...

Hi all, I am proposing the integration of a backend targeting the RISC-V ISA. RISC-V is a free and open instruction set architecture that was originally developed at UC Berkeley. Future development of the ISA specification will be handled by the 501(c)(6) non-profit RISC-V Foundation and its members <https://riscv.org/membership/?action=viewlistings>. You can find much more information at