search for: d21251

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2016 Jun 16
2
[RFC] Allow loop vectorizer to choose vector widths that generate illegal types
...;free" from the legalizer instead. There are two potential road-blocks I see - the cost-model, and the legalizer. To make this work, we need to: a) Model the cost of operations on illegal types better. Right now, what we get is sometimes completely ridiculous (e.g. see http://reviews.llvm.org/D21251). b) Make sure the cost model actually stops us when the VF becomes too large. This is mostly a question of correctly estimating the register pressure. In theory, that should not be a issue - we already rely on this estimate to choose the interleaving factor, so using the same logic to upper-bound...
2016 Jun 15
8
[RFC] Allow loop vectorizer to choose vector widths that generate illegal types
...;free" from the legalizer instead. There are two potential road-blocks I see - the cost-model, and the legalizer. To make this work, we need to: a) Model the cost of operations on illegal types better. Right now, what we get is sometimes completely ridiculous (e.g. see http://reviews.llvm.org/D21251). b) Make sure the cost model actually stops us when the VF becomes too large. This is mostly a question of correctly estimating the register pressure. In theory, that should not be a issue - we already rely on this estimate to choose the interleaving factor, so using the same logic to upper-bound...
2016 Jun 16
2
[RFC] Allow loop vectorizer to choose vector widths that generate illegal types
...ean that we should be duplicating every optimization the SelectionDAG makes. Of course the cost model is only a rough approximation. What I do want the (generic) cost model to do, however, is provide a more-or-less precise approximation of legalization costs. To be concrete, http://reviews.llvm.org/D21251 is a first step in that direction. Do you think this is something the cost model should not be doing? Regarding loop widening - see my email to Dibyendu for what I meant. For mixed-type loops, it really depends. Let's say you have a mixed-type loop, with i32 and i64, and 256-bit registers. Wou...