search for: d1_d2

...re is no "most super" register? I'm having a hard time thinking up > how one would design such an ISA. The ARM NEON D-registers are 64 bits each. NEON has vld1 instructions that can load 2, 3, or 4 consecutive D-registers. Two consecutive D-registers is represented by the D0_D1, D1_D2, D2_D3, ... super-registers. As you can see, D1 has two super-registers, neither is more super than the other. We similarly define triples and quads of consecutive D-registers. NEON also has 128-bit vector instructions operating on even-odd pairs of D-registers, so the actual register names we us...

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> A MachineOperand has both a getReg() and a getSubReg() interface. >> For a physical register operand, is getReg() guaranteed to be the >> "most super" register with getSubReg() providing the specific >> subregister information for the operand? If so then for my current >> purposes it seems I

...t it decides to call an encoding constraint, LLVM's concept of a physical register is usually a bit broader, but more consistent. We will normally define physical registers for all reasonable encoding constraints on register operands. For example, the LLVM ARM target has physical registers like D1_D2 which don't exist in the ISA. In a target with many encoding constraints like that, some registers can have a high number of super-registers, and even more aliases. On the last count, some of the ARM NEON registers had more than 40 aliasing registers. The register allocator uses register unit...

...d1.64 {d1, d2}, [r0] The instruction loads two d-registers, but they must be consecutive. ARM also names even-odd pairs of d-registers, q0 = {d0, d1}, but odd-even pairs have no other name than {d1, d2}. LLVM models the sequence constraint as a single super-register, so we define pseudo-registers D1_D2, D3_D4, … in addition to the existing Q0, Q1, … From the register allocator's point of view, the vld1.64 instruction has two operands: a GPR operands for the address, and a DPair operand representing the two consecutive d-registers. This model makes it easy to handle register sequence constrai...

...t it decides to call an encoding constraint, LLVM's concept of a physical register is usually a bit broader, but more consistent. We will normally define physical registers for all reasonable encoding constraints on register operands. For example, the LLVM ARM target has physical registers like D1_D2 which don't exist in the ISA. > > In a target with many encoding constraints like that, some registers can have a high number of super-registers, and even more aliases. On the last count, some of the ARM NEON registers had more than 40 aliasing registers. > > The register allocato...