Displaying 3 results from an estimated 3 matches for "d194".
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2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...(d11):u23, u52<ECX>(d4):]
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> .
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> .
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> .
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> s61: CMP32mr [d62<EFLAGS>!(d58,d80,u205):, u63<RDI>(+d194):u55,
> u64<RSI>(d57):, u65<ECX>(d50):]
>
> This is a test case I was interested in because it shows the partial
> register redefinition scenario in X86 for which more register units
> needed to be added. I have a hacky fix for this in TableGen code which
> adds m...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
....
>>>
>>> .
>>>
>>> .
>>>
>>> s61: CMP32mr [d62<EFLAGS>!(d58,d80,u205):, u63<RDI>(+d194):u55,
>>> u64<RSI>(d57):, u65<ECX>(d50):]
>>>
>>> This is a test case I was interested in because it shows the partial
>>> register redefinition scenario in X86 for which more register units needed
>>> to be added. I have a hacky fix for this...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof,
Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts.
Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a