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*RESEND* due to exceeding the mailinglists limit for attachment size. Hi, I''m trying to get secondary vga-passthrough on a HVM guest to work with a AMD HD6570 and the native kernel radeon driver and kernel modesetting. So the guest still gets the emulated stdvga or cirrus device(used in my case here) as primary/boot vga adapter. - When i don''t passthrough the radeon card, the

...or(d1 in 0:n){ for(d2 in 0:n){ for(d3 in 0:n){ for(d4 in 0:n){ for(d5 in 0:n){ for(d6 in 0:n){ for(d7 in 0:n){ for(d8 in 0:n){ for(d9 in 0:n){ for(d10 in 0:n){ for(d11 in 0:n){ for(d12 in 0:n){ for(d13 in 0:n){ for(d14 in 0:n){ for(d15 in 0:n){ for(d16 in 0:n){ for(d17 in 0:n){ for(d18 in 0:n){ for(d19 in 0:n){ for(d20 in 0:n){ list=c(d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20) }}}}}}}}}}}}}}}}}}}} [[alternative HTML version deleted]]

..." vld1.16 {d16}, [%[b]]!\n" + " vld1.16 {d20}, [%[a]]!\n" + " subs %[remainder], %[remainder], #4\n" + " vmull.s16 q0, d16, d20\n" + " beq 5f\n" + " b 4f\n" + "1:" + " vld1.16 {d16, d17, d18, d19}, [%[b]]!\n" + " vld1.16 {d20, d21, d22, d23}, [%[a]]!\n" + " subs %[len], %[len], #16\n" + " vmull.s16 q0, d16, d20\n" + " vmlal.s16 q0, d17, d21\n" + " vmlal.s16 q0, d18, d22\n" + " vmlal.s16 q0, d19, d23\n"...

In hvm enviroment, acpi failed. why? centos5.1 =================================================== [root@hvm001 ~]# xm dmesg __ __ _____ _ ____ ___ ____ _ ____ \ \/ /___ _ __ |___ / / | |___ \ / _ \___ \ ___| | ___| \ // _ \ \047_ \ |_ \ | | __) |_| (_) |__) | / _ \ |___ \ / \ __/ | | | ___) || |_ / __/|__\__, / __/ | __/ |___) | /_/\_\___|_| |_| |____(_)_(_)_____| /_/_____(_)___|_|____/

...t.data[i] = a.data[i] * b.data[i]; return result; } void TestVec4Multiply(vec4& a, vec4& b, vec4& result) { result = a * b; } With -O3 the loop gets vectorized and the code generated looks optimal: __Z16TestVec4MultiplyR4vec4S0_S0_: @ BB#0: vld1.32 {d16, d17}, [r1] vld1.32 {d18, d19}, [r0] vmul.f32 q8, q9, q8 vst1.32 {d16, d17}, [r2] bx lr However if I replace the operator* with a NEON intrinsic implementation (I know the vectorizer figured out optimal code in this case anyway, but that wasn't true for my real situation) then the temporary "result" seems to b...

...%tmp3, <4 x float>* %C ret void } declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone I've got following code generated: ... vmaxf32: @ @vmaxf32 @ BB#0: vld1.64 {d16, d17}, [r2] vld1.64 {d18, d19}, [r1] vmax.f32 q8, q9, q8 vst1.64 {d16, d17}, [r0] bx lr ... Now if use <16 x float> vectors instead of <4 x float>: define void @vmaxf32(<16 x float> *%C, <16 x float>* %A, <16 x float>* %B) nounwind { %tmp1 = load <16 x float>* %A %tmp2 = load &lt...

On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote: > Hi all, > I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched > > The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. A bug for this is welcome. Pretty soon, I’ll

Hi all, I meet this problem when compiling the TREAM benchmark ( http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. so I rewrite a simple code as attached link (foo.c), and compiled with two different methods: *method A:* *$clang -O3 foo.c -static -S

From: Jyri Sarha <jsarha at ti.com> I optimized Speex resampler for NEON capable ARM CPUs. The first patch should speed up resampling on any platform that can spare the increased memory usage. It would be nice to have these merged to the master branch. Please let me know if there is anything I can do to help the the merge. The patches have been rebased on top of master branch in

...ileged (18) attempt to map I/O space 00000000 > (XEN) mm.c:645:d18 Non-privileged (18) attempt to map I/O space 000000c0 > (XEN) mm.c:645:d18 Non-privileged (18) attempt to map I/O space 0000009f > (XEN) mm.c:645:d18 Non-privileged (18) attempt to map I/O space 000000e0 > (XEN) mm.c:645:d19 Non-privileged (19) attempt to map I/O space 00000000 > (XEN) mm.c:645:d19 Non-privileged (19) attempt to map I/O space 000000c0 > (XEN) mm.c:645:d19 Non-privileged (19) attempt to map I/O space 0000009f These addresses are re-occurring, but I can''t really say whether it''s r...

...x, roots2, suffix3) d10 = mytwo(prefix2, roots2, suffix) d11 = mytwo(prefix2, roots2, suffix2) d12 = mytwo(prefix2, roots2, suffix3) d13 = myone(prefix, roots) d14 = myone(prefix2, roots) d15 = myone(prefix, roots2) d16 = myone(prefix2, roots2) d17 = myone(roots, suffix) d18 = myone(roots, suffix2) d19 = myone(roots, suffix3) d20 = myone(roots2, suffix) d21 = myone(roots2, suffix2) d22 = myone(roots2, suffix3) d23 = myone(state, roots) d24 = myone(city, roots) d25 = myone(cityst, roots) d26 = myone(inscompany, roots) d27 = myone(state, roots2) d28 = myone(city, roots2) d29 = myone(cityst, roots2)...

Just posted: http://blogs.sun.com/roch/entry/nfs_and_zfs_a_fine ____________________________________________________________________________________ Performance, Availability & Architecture Engineering Roch Bourbonnais Sun Microsystems, Icnc-Grenoble Senior Performance Analyst 180, Avenue De L''Europe, 38330, Montbonnot Saint

...rsioning for alias checks. test.c:11: note: === vect_do_peeling_for_loop_bound ===Setting upper bound of nb iterations for epilogue loop to 14 test.c:11: note: LOOP VECTORIZED. The result is a very concise and very dense code: vld1.8 {d28[], d29[]}, [r5] vld3.8 {d16, d18, d20}, [r9]! vld3.8 {d17, d19, d21}, [r9] vmvn q3, q8 vmvn q15, q9 vmvn q8, q10 vsub.i8 q11, q3, q14 vsub.i8 q12, q15, q14 vsub.i8 q13, q8, q14 vst3.8 {d22, d24, d26}, [r8]! vst3.8 {d23, d25, d27}, [r8] cheers, --renato -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org...

...e <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone > > I've got following code generated: > > ... > vmaxf32: @ @vmaxf32 > @ BB#0: > vld1.64 {d16, d17}, [r2] > vld1.64 {d18, d19}, [r1] > vmax.f32 q8, q9, q8 > vst1.64 {d16, d17}, [r0] > bx lr > ... > > Now if use <16 x float> vectors instead of <4 x float>: > > define void @vmaxf32(<16 x float> *%C, <16 x float>* %A, <16 x float>* %B)...

On 21 September 2012 09:28, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > declare <16 x float> @llvm.arm.neon.vmaxs.v16f32(<16 x float>, <16 x float>) nounwind readnone > > llc fails with following message: > > SplitVectorResult #0: 0x2258350: v16f32 = llvm.arm.neon.vmaxs 0x2258250, 0x2258050, 0x2258150 [ORD=3] [ID=0] > > LLVM ERROR: Do not

...e <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone > > I've got following code generated: > > ... > vmaxf32: @ @vmaxf32 > @ BB#0: > vld1.64 {d16, d17}, [r2] > vld1.64 {d18, d19}, [r1] > vmax.f32 q8, q9, q8 > vst1.64 {d16, d17}, [r0] > bx lr > ... > > Now if use <16 x float> vectors instead of <4 x float>: > > define void @vmaxf32(<16 x float> *%C, <16 x float>* %A, <16 x float>* %B)...

...x float> %tmp3, <16 x float>* %C ret void } and llc generates following code: vaddf32: @ @vaddf32 @ BB#0: add r12, r1, #48 add r3, r2, #32 vld1.64 {d20, d21}, [r3, :128] add r3, r2, #48 vld1.64 {d16, d17}, [r2, :128] add r2, r2, #16 vld1.64 {d18, d19}, [r1, :128] vld1.64 {d26, d27}, [r12, :128] add r12, r1, #32 vld1.64 {d24, d25}, [r3, :128] add r1, r1, #16 vadd.f32 q11, q9, q8 vld1.64 {d28, d29}, [r12, :128] vadd.f32 q9, q13, q12 vadd.f32 q8, q14, q10 vld1.64 {d20, d21}, [r2, :128] vld1.64 {d24, d25}, [r1, :128] add r1, r0, #48 vad...

...-mfloat-abi=hard -mllvm -enable-misched Scale: movw r12, :lower16:c movw r2, :lower16:b movw r3, #9216 movt r12, :upper16:c mov r1, #0 vmov.f64 d16, #3.000000e+00 movt r2, :upper16:b movt r3, #244 .LBB0_1: add r0, r12, r1 * vldr d17, [r0]* * vldr **d18**, [r0, #8] * vmul.f64 d17, d17, d16 * vldr **d19**, [r0, #16]* * vldr **d20**, [r0, #24]* add r0, r2, r1 vmul.f64 d18, d18, d16 add r1, r1, #32 cmp r1, r3 vmul.f64 d19, d19, d16 vmul.f64 d20, d20, d16 vstmia r0, {d17, d18, d19, d20} bne .LBB0_1 bx lr this is just because A9's per-operand machine model is not implemented well? By the way, why...

...on.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone >> >> I've got following code generated: >> >> ... >> vmaxf32: @ @vmaxf32 >> @ BB#0: >> vld1.64 {d16, d17}, [r2] >> vld1.64 {d18, d19}, [r1] >> vmax.f32 q8, q9, q8 >> vst1.64 {d16, d17}, [r0] >> bx lr >> ... >> >> Now if use <16 x float> vectors instead of <4 x float>: >> >> define void @vmaxf32(<16 x float> *%C, <16 x float&gt...

...lt;imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,de...