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Hi Jan, Attached patch dumps io page fault flags. The flags show the reason of the fault and tell us if this is an unmapped interrupt fault or a DMA fault. Thanks, Wei signed-off-by: Wei Wang <wei.wang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel

...mory allocation problems. Thanks for your time and consideration. for(d1 in 0:n){ for(d2 in 0:n){ for(d3 in 0:n){ for(d4 in 0:n){ for(d5 in 0:n){ for(d6 in 0:n){ for(d7 in 0:n){ for(d8 in 0:n){ for(d9 in 0:n){ for(d10 in 0:n){ for(d11 in 0:n){ for(d12 in 0:n){ for(d13 in 0:n){ for(d14 in 0:n){ for(d15 in 0:n){ for(d16 in 0:n){ for(d17 in 0:n){ for(d18 in 0:n){ for(d19 in 0:n){ for(d20 in 0:n){ list=c(d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,d20) }}}}}}}}}}}}}}}}}}}} [[alternative HTML version deleted]]

> This isn't really my area of expertise, but I think you're messing up > your RegisterClass definition. Look at how ARM defines DTriple. DTriple is untyped :) , because we do not have any valut type which defines 3xi64. However, the paired register needs to have type. Fabian, what are the definitions of ER and DR register classes? -- With best regards, Anton Korobeynikov Faculty

...ER and DR register classes? Hi Anton, here are the definitions of these register classes: // Data register class def DR : RegisterClass<"TriCore", [i32], 32, (add D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15)>; // Extended-size data register class def ER : RegisterClass<"TriCore", [i64], 32, (add E0, E2, E4, E6, E8, E10, E12, E14)> { let SubRegClasses = [(DR sub_even, sub_odd)]; } And the DX and EX registers are defined this way: def D0 : TriCoreReg<0,...

...avoid that dotplot sorts my x-values. They are in the correct order in the data.frame and the connections between the x-y values follows this order, but the placement of the x-values on the x-axis is re-ordered. In the following example, the order should be "d1", "d8" and "d15". However, this script places "d8" at the highest x position. Any help is appreciated. Subj <- rep(1:4,each=3) Time <- rep(c("d1","d8","d15"),4) Conc <- 1:12 df <- data.frame(Subj,Time,Conc) dotplot(Conc ~ Time | Subj, data = df,...

On 11/08/2013 09:12 AM, Steve Capper wrote: > + > +/* > + * x19-x28 are callee saved, also save fp, lr, sp. > + * d8-d15 are also callee saved. > + */ > + > +struct __jmp_buf { > + uint64_t __gregs[13]; > + uint64_t __fpregs[8]; > +}; > + Since the index of these arrays have no connection with what is stored in them, they should be named fields in the structure, not an array. Do we need the fpr...

...d4 d5 d6 272462.52504 189076.44195 95736.37691 47830.40918 23593.41513 12409.42279 d7 d8 d9 d10 d11 d12 5977.28418 2887.81182 1408.06198 629.46550 368.87030 197.00823 d13 d14 d15 106.22607 29.75633 14.29115 $EDOF2 [1] NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA $EDOF3 d1 d2 d3 d4 d5 d6 2.079385e+05 1.039658e+05 5.197938e+04 2.598619e+04 1.298959e+04 6.491297e+03 d7 d8 d9...

...TACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...reducing the context switch frequency of the FPU register. For nomal case, say Y. @@ -75,11 +75,11 @@ choice if its cache way size is larger than page size. You can specify the CPU type direcly or choose CPU_V3 if unsure. - A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. - A kernel built for N15 is able to run on N15 or D15. - A kernel built for D10 is able to run on D10 or D15. - A kernel built for D15 is able to run on D15. - A kernel built for N13 is able to run on N15, N13 or D15. + A kernel built for N10...

...TACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $...

...32:%vreg253 4496B %vreg261<def> = FMUL_D32 %vreg247, %vreg248; AFGR64:%vreg261,%vreg247,%vreg248 4512B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use> 4528B %D6<def> = COPY %vreg243; AFGR64:%vreg243 4544B JAL <ga:@sin>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7 >, %RA<imp-def,dead>, %D6<imp-use,kill>, %SP<imp-def>, %D0<imp-def> 4560B ADJCALLSTACKUP 16, 0, %SP<imp-def>, %SP<imp-use> 4576B %vreg262<def> = COPY %D0<kil...

On Fri, Nov 08, 2013 at 09:24:06AM -0800, H. Peter Anvin wrote: > On 11/08/2013 09:12 AM, Steve Capper wrote: > > + > > +/* > > + * x19-x28 are callee saved, also save fp, lr, sp. > > + * d8-d15 are also callee saved. > > + */ > > + > > +struct __jmp_buf { > > + uint64_t __gregs[13]; > > + uint64_t __fpregs[8]; > > +}; > > + > > Since the index of these arrays have no connection with what is stored > in them, they should be named fields i...

Steve Capper dixit: >> Do we need the fpregs saved even though klibc doesn't do fp? >For gcc targetting Aarch64, We can only guarantee that d8-d15 are >left alone when -mgeneral-regs-only is supplied for building klibc >and any software linked against klibc. I would much prefer to We can enforce this in klcc, just like -mregparm=3 is used by the i386 target. bye, //mirabilos -- ?Cool, /usr/share/doc/mksh/examples/uhr.gz ist ja ein Gr...

To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The

...vdev, we have something like this: Disk0 Disk1 Disk2 Disk3 NewDisk <<P00 D00 D01 D02 U P01 D03 D04 D05 U P02 D06>> <<P03 D07>> U <<P04 D08>> <<P05 D09 U P06 D10 D11 D12>> U <<P07 D13 D14 D15>> U Then we start moving data, but we need to beging from the start: Disk0 Disk1 Disk2 Disk3 NewDisk <<N00 D00 D01 D02 D03 N01 D04 D05 D06>> <<P03 D07>> * U U U U <<P04 D08>> <<P05 D09 U P06 D10 D11 D1...

Fabian, > here are the definitions of these register classes: > > // Data register class > def DR : RegisterClass<"TriCore", [i32], 32, > (add D0, D1, D2, D3, D4, D5, D6, D7, > D8, D9, D10, D11, D12, D13, D14, D15)>; > > // Extended-size data register class > def ER : RegisterClass<"TriCore", [i64], 32, > (add E0, E2, E4, E6, E8, E10, E12, E14)> { > let SubRegClasses = [(DR sub_even, sub_odd)]; > } > > And the DX and EX registers are defined...

I would like to calculate vector from existing value e.g v <- 1000 s <- 30 d1 <- v-s d1 <- 970 d2 <- d1 -s d2 <- 940 d 3 <- d2-s d3 <- 910 : : d15 <- ..... so how I should get vector of length 15 d < - 970,940 , 910 , ....... -- View this message in context: http://r.789695.n4.nabble.com/vector-subtraction-tp4573299p4573299.html Sent from the R help mailing list archive at Nabble.com.

...f these register classes: >>> >>> // Data register class >>> def DR : RegisterClass<"TriCore", [i32], 32, >>> (add D0, D1, D2, D3, D4, D5, D6, D7, >>> D8, D9, D10, D11, D12, D13, D14, D15)>; >>> >>> // Extended-size data register class >>> def ER : RegisterClass<"TriCore", [i64], 32, >>> (add E0, E2, E4, E6, E8, E10, E12, E14)> { >>> let SubRegClasses = [(DR sub_even, sub_odd)]; >>> }...

...prefix2, roots, suffix3) d7 = mytwo(prefix, roots2, suffix) d8 = mytwo(prefix, roots2, suffix2) d9 = mytwo(prefix, roots2, suffix3) d10 = mytwo(prefix2, roots2, suffix) d11 = mytwo(prefix2, roots2, suffix2) d12 = mytwo(prefix2, roots2, suffix3) d13 = myone(prefix, roots) d14 = myone(prefix2, roots) d15 = myone(prefix, roots2) d16 = myone(prefix2, roots2) d17 = myone(roots, suffix) d18 = myone(roots, suffix2) d19 = myone(roots, suffix3) d20 = myone(roots2, suffix) d21 = myone(roots2, suffix2) d22 = myone(roots2, suffix3) d23 = myone(state, roots) d24 = myone(city, roots) d25 = myone(cityst, roots)...