Displaying 2 results from an estimated 2 matches for "d0fd4e45".
2011 Mar 29
0
[LLVMdev] IR in SSA form?
On 3/29/11 12:26 PM, George Baah wrote:
> Hi All,
> When I run the following command
> llvm-gcc -03 -emit-llvm test.cpp -c -o test.bc or llvm-gcc -emit-llvm
> test.cpp -c -o test.bc
>
> on the program test.cpp, the IR representation is not in SSA form.
> I do not see any phi functions.
Actually, it is in SSA form (or more precisely, the virtual registers
are in SSA form;
2011 Mar 29
3
[LLVMdev] IR in SSA form?
Hi All,
When I run the following command
llvm-gcc -03 -emit-llvm test.cpp -c -o test.bc or llvm-gcc -emit-llvm
test.cpp -c -o test.bc
on the program test.cpp, the IR representation is not in SSA form.
I do not see any phi functions.
program: test.cpp
int main(int argc, char **argv)
{
int a[2],i,j;
for(i=0;i<2;i++)
{
a[i] = i;
}
return a[1];
}
Any clarifications will be