search for: d0ced94ca54c

...g the instmem. In that case I wonder if this shouldn't be moved into an operation that is implemented by the backing memory pool and be a noop where the cache doesn't need explicit flushing. > diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h > index d0ced94ca54c..274b4460bb03 100644 > --- a/drivers/gpu/drm/nouveau/core/os.h > +++ b/drivers/gpu/drm/nouveau/core/os.h > @@ -38,4 +38,21 @@ > #endif /* def __BIG_ENDIAN else */ > #endif /* !ioread32_native */ > > +#if defined(__arm__) > + > +#define nv_cpu_cache_flush_area(va, size...

...s shouldn't be moved into an operation that >> is implemented by the backing memory pool and be a noop where the cache >> doesn't need explicit flushing. >> >> > diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h >> > index d0ced94ca54c..274b4460bb03 100644 >> > --- a/drivers/gpu/drm/nouveau/core/os.h >> > +++ b/drivers/gpu/drm/nouveau/core/os.h >> > @@ -38,4 +38,21 @@ >> > #endif /* def __BIG_ENDIAN else */ >> > #endif /* !ioread32_native */ >> > >> > +#if defined(_...

...re Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/core/os.h | 17 +++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bo.c | 8 ++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h index d0ced94ca54c..274b4460bb03 100644 --- a/drivers/gpu/drm/nouveau/core/os.h +++ b/drivers/gpu/drm/nouveau/core/os.h @@ -38,4 +38,21 @@ #endif /* def __BIG_ENDIAN else */ #endif /* !ioread32_native */ +#if defined(__arm__) + +#define nv_cpu_cache_flush_area(va, size) \ +do { \ + phys_addr_t pa = virt_to_p...

...ase I wonder if this shouldn't be moved into an operation that > is implemented by the backing memory pool and be a noop where the cache > doesn't need explicit flushing. > > > diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h > > index d0ced94ca54c..274b4460bb03 100644 > > --- a/drivers/gpu/drm/nouveau/core/os.h > > +++ b/drivers/gpu/drm/nouveau/core/os.h > > @@ -38,4 +38,21 @@ > > #endif /* def __BIG_ENDIAN else */ > > #endif /* !ioread32_native */ > > > > +#if defined(__arm__) > > + > &...

...oved into an operation that >>> is implemented by the backing memory pool and be a noop where the cache >>> doesn't need explicit flushing. >>> >>> > diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h >>> > index d0ced94ca54c..274b4460bb03 100644 >>> > --- a/drivers/gpu/drm/nouveau/core/os.h >>> > +++ b/drivers/gpu/drm/nouveau/core/os.h >>> > @@ -38,4 +38,21 @@ >>> > #endif /* def __BIG_ENDIAN else */ >>> > #endif /* !ioread32_native */ >>> > >...

This small series introduces TTM helper functions as well as Nouveau hooks that are needed to ensure buffer coherency on ARM. Most of this series is a forward-port of some patches Lucas Stach sent last year and that are also needed for Nouveau GK20A support: http://lists.freedesktop.org/archives/nouveau/2013-August/014026.html Another patch takes care of flushing the CPU write-buffer when