search for: d0_d1

...gt; there is no "most super" register? I'm having a hard time thinking up > how one would design such an ISA. The ARM NEON D-registers are 64 bits each. NEON has vld1 instructions that can load 2, 3, or 4 consecutive D-registers. Two consecutive D-registers is represented by the D0_D1, D1_D2, D2_D3, ... super-registers. As you can see, D1 has two super-registers, neither is more super than the other. We similarly define triples and quads of consecutive D-registers. NEON also has 128-bit vector instructions operating on even-odd pairs of D-registers, so the actual register name...

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: >> A MachineOperand has both a getReg() and a getSubReg() interface. >> For a physical register operand, is getReg() guaranteed to be the >> "most super" register with getSubReg() providing the specific >> subregister information for the operand? If so then for my current >> purposes it seems I