Displaying 2 results from an estimated 2 matches for "d08566a0".
2019 Jan 22
2
Different SelectionDAGs for same CPU
Hi,
I used 2 different compilers to compile the same IR for the same custom target.
The LLVM IR code is
define i32 @_Z9test_mathv() #0 {
%a = alloca i32, align 4
%1 = load i32, i32* %a, align 4
ret i32 %1
}
Before instruction selection, the Selection DAGs are the same:
Optimized legalized selection DAG: %bb.0 '_Z9test_mathv:'
SelectionDAG has 7 nodes:
t0: ch = EntryToken
t4:
2019 Jan 26
2
Different SelectionDAGs for same CPU
...u
should find it pretty quickly though, even if they used some other
method. There don't tend to be many uses of that particular node.
Cheers.
Tim.
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