search for: cyclon

Hi there: We have recently inherited a circa 1996 SGI Indy Colorbus Cyclone running on Irix. Our intention is to use this unit to drive our Canon CLC900 Scanner Copier and make it accessible to our Windows Network. At the moment, our Windows Network does not "see" the Cyclone & vice versa. I have read that installing some kind of Windows Samba client onto...

...] comment = Spreadsheets path = /d0/shares/spreadsheets read only = No browseable = No guest ok = No [work] comment = Data from Work path = /d0/shares/work read only = No browseable = No guest ok = No 3. vi /etc/hosts 192.168.110.50 snow 192.168.110.3 cyclone 4. testparm SNOW# testparm Load smb config files from /etc/samba/smb.conf Processing section "[software]" Processing section "[spreadsheets]" Processing section "[work]" Loaded services file OK. 'winbind separator = +' might cause problems with group membersh...

...r ISR/6: Time went backwards: -9953000 4470550000000 47000 4470560000000 Timer ISR/5: Time went backwards: -9951000 4474600000000 49000 4474610000000 I looked at the archives and noticed this was reported when running under VMware, but I see this happening with only xen and dom0. The system has a Cyclone timer, and I am looking at using the Cyclone timer to avoid the TSC drift, but while it is easy to add to xen, all the cyclone support has been removed from linux. Are there any plans to restore Cyclone or HPET support to linux, and add it to xen, to eliminate this kind of problem? I have some...

Hi, I need to derive a time series that represents the first derivative of an original time series. The function coefDeriv in the cyclones package seemed to be the ticket, but I'm not sure if I am interpreting the output of the function correctly...or even using the function correctly. This is a snipbit of what I've been trying: -------- library(cyclones) ## read in my 1-column of values, each line is a different time step...

...s? is it in "configure" file? Thanks, Andr? Costa PS: I wasn't getting to communicate with the LEON in FPGA by serial interface, but I discovered the problem. The number code of my FPGA was slightly different. The difference was just in mapping of pins. When I changed of FPGA (to a cyclone), I got to run a hello word! For while I am using the cyclone, but after I will need to map all the pins. -- Andr? Costa Gerente T?cnico Projeto BrazilIP LSC IC-UNICAMP Cel: + 55 13 9201 1870 http://www.brazilip.org.br/ -------------- next part -------------- An HTML attachment was scrubbed......

Hi all, As of r232885 I've removed the argument-less TargetMachine::getSubtarget and TargetMachine::getSubtargetImpl. For the targets that aren't completely independent of this I've gone ahead and left a non-virtual version of the function in the target specific TargetMachine. What this means in practice is that those targets can only use a bare getSubtarget call in their target

On Fri, May 19, 2017 at 4:01 PM Adam Nemet via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I will run it on Cyclone/AArch64 next week. > FYI, we're still waiting on these Adam... -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170530/7cb390ca/attachment.html>

Ping. Can I assume that we're ok with this interface proposal then? Amara -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140127/49962cbc/attachment.html>

Hi, I've got pxelinux 2.00 working to boot rh 7.3, 8.0, and phoebe-beta pxe install images but I've recently tried to load the rh 9 pxe install images and I get this.. 4000 AX:0208 BX:0200 CX:0002 DX:0000. Any thoughts? Thanks aaron

Hi, I was looking at some AArch64 benchmarks and noticed some simple cases where addresses are being folded into the address mode computations and was curious as to why. In particular, consider the following simple example: void f2(unsigned long *x, unsigned long c) { x[c] *= 2; } This generates: lsl x8, x1, #3 ldr x9, [x0, x8] lsl x9, x9, #1 str x9, [x0, x8] Given the two

[resending to correct llvm-dev address] Hi, I’d like to start enabling the loop data prefetch pass for Cyclone (an ARM64 subtarget). AFAICT, you can’t really add passes specifically to a subtarget but only to a target. This makes sense because in the new world, you could have different subtargets per function. I just want to make sure my understanding is correct. My plan is to add the pass for the targ...

...gcc/2008-06/msg00385.html > There is a new branch for converting gcc to C++. > > Best regards, > --Edwin The sad thing is that they seem to be replacing one unsafe language with another, presumably with enormous effort. The only hopeful sign in that thread is the proposal for using Cyclone instead, starting here:http://gcc.gnu.org/ml/gcc/2008-06/msg00502.html But it is summarily tossed out, without examination: http://gcc.gnu.org/ml/gcc/2008-06/msg00644.html If all we can ever use are languages that everyone knows, there will be no progress. -- hendrik

Hi, Have you seen this: http://gcc.gnu.org/ml/gcc/2008-06/msg00385.html There is a new branch for converting gcc to C++. Best regards, --Edwin

...uot;expected" code is easy to get by checking the number of uses. This > > may be desirable on some micro-architectures depending on the cost of > > the various loads and stores. > > As you say, very microarchitecture-dependent. The code produced is > probably optimal for Cyclone ("[x0, x8]" is no more expensive than > "[x8]" and the "lsl" is slightly cheaper than the complicated "add"). > If I'm reading the Cortex-A57 optimisation guide correctly, the same > reasoning applies there too. > > Cheers. > > Tim....

...hat, Eric replied me here's a proposal toward using '-march' instead of '-mcpu'. As it's half a year later from original proposal, some background may changes. One thing worth to mention is, during this time, Apple Contributed its backend and introduced another new CPU type: cyclone. Now, AArch64 target supports 4 kinds of CPU types: cyclone, cortex-a53, cortex-a57 and generic. First three cover full feature from fp to crypto, and for generic, only fp and neon are enabled by default. As time goes by, more and more CPU types will be introduced with different combination of fea...

...pos = "http://cran.cnr.berkeley.edu/") #failPackages is the "black list". Things get inserted for various reasons #rejected because they don't build on my system as of July, 2005, or are obviously not needed failPackages1 <- c("BRugs","tclkt2","cyclones","rpvm","ncdf","gtkDevice","gap","gnomeGUI","mimR","pathmix","rcdd","rgdal","rpvm","Rmpi","RQuantLib","RMySQL", "RNetCDF","RODBC","ROracl...

Dear all: Does anyone has harmonic regresssion analysis package written in R (to be used in Windows platform) ? Thanks _______________________________________ YM - Â÷½u°T®§ ´Nºâ§A¨S¦³¤Wºô¡A§AªºªB¤Í¤´¥i¥H¯d¤U°T®§µ¹§A¡A·í§A¤Wºô®É´N¯à¥ß§Y¬Ý¨ì¡A¥ô¦ó»¡¸Ü³£ÉN¨«¥¢¡C http://messenger.yahoo.com.hk [[alternative HTML version deleted]]

I've plugged in two 3com OfficeConnect 10/100 3CSOHO100B-TX in my freebsd 4.8 box and they are not detected. Do I have to enable some support in the kernel ? Cheers Hannes

Hi all, A bunch of us met at EuroLLVM to discuss the planned merge of the two current AArch64 backends in the tree. The primary question was which backend should form the basis of the merge (since the core .td files aren't directly mergeable), with code being cherry-picked from the other on a case-by-case basis. There were factors to consider both ways, but I think the key points of interest

...ugs are fixed upstream. This includes NEON instruction selection. § I’m still running testing to validate, but this can be thought of as complete. o [DONE] Support for no fpu/no neon/ no crc o [DONE] A53 scheduler o [DONE] Inline assembly o [DONE] Predefines o [DONE] Conditionalise cyclone/Darwin § Only the “LDR q” -> “LDP d, d” splitting pass to really conditionalise – only benchmarks will really show though. o [?] ADRP CSE § This optimization, being worked on by Jiangning, has been half ported to ARM64. But it hasn’t been committed to AArch64 yet, so it can’t be consider...