Displaying 2 results from an estimated 2 matches for "cvtss2sd".
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vcvtss2sd
2011 Dec 28
1
[LLVMdev] Codegen for vector float->double cast fails on x86 above SSE3
...ret void
}
The code should load a <2 x float> vector from %in, fpext cast it to a
<2 x double>, and do an unaligned store (movupd) of the result to
%out. This works as expected on earlier SSE targets, generating this
with llc -mcpu=core2:
movss (%rdi), %xmm1
movss 4(%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
unpcklpd %xmm0, %xmm1 ## xmm1 = xmm1[0],xmm0[0]
movupd %xmm1, (%rsi)
ret
Load both, cast float to double (cvtss2sd), pack vectors, and store.
But with llc -mcpu=penryn or greater, it yields nonsense:
movq (%rdi), %xmm0
pshufd $16, %xmm0, %xmm0 ##...
2009 Feb 23
1
[LLVMdev] 2.5 Pre-release2 available for testing
On Mon, Feb 23, 2009 at 12:12 AM, Aaron Gray <
aaronngray.lists at googlemail.com> wrote:
> On Sun, Feb 22, 2009 at 11:15 PM, Anton Korobeynikov <
> anton at korobeynikov.info> wrote:
>
>>
>> Actually its [configure-stage3-intl] where its hanging.
>>
>> This can easily be due to inline FP math in the stdlib headers. For
>> example - I had to