search for: custominserter

Displaying 9 results from an estimated 9 matches for "custominserter".

2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
..."# OR_A_oo", [(set FPUaROUTADDRegisterClass:$FA_ROUTADD,(or FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB))],NoItinerary> {let usesCustomInserter = 1;} The instructions selection and registers allocation are performed with the pseudo. %4:fpuaoffsetclass = LOAD_A_r @a; FPUaOffsetClass:%4 %5:fpuaoffsetclass = LOAD_A_r @b; FPUaOffsetClass:%5 %6:fpuaroutaddregisterclass = OR_A_oo killed %5, killed %4, implicit-def dead...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
Hi, I've instruction scheduling problem that I cannot further investigate by myself... Could someone give me some clues? After Instruction selection, here is part of the generated instruction. NOP MOV_AB_ro @s1, %fab_roff0 %6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6 MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5 MOVSUTO_A_iSLo 24575, def %7;
2018 Mar 29
4
Mapping virtual registers to physical registers
...ROFF0+FrameIndex); destination.setIsDef(true); TII->loadRegFromStackSlot(*MBB, MI, destinationReg, FrameIndex, &CLP::FPUaOffsetClassRegClass, TRI); The code after customInserter seems valid but the compilation later hang-up in an infinite loop in procedure computeVirtRegs(); of pass LiveIntervals::runOnMachineFunction. In other targets, I've seen an example with a setIsDef(true) for such physically mapped register. Is there something missing in my code (register other...
2018 Mar 30
0
Mapping virtual registers to physical registers
...ROFF0+FrameIndex); destination.setIsDef(true); TII->loadRegFromStackSlot(*MBB, MI, destinationReg, FrameIndex, &CLP::FPUaOffsetClassRegClass, TRI); The code after customInserter seems valid but the compilation later hang-up in an infinite loop in procedure computeVirtRegs(); of pass LiveIntervals::runOnMachineFunction. In other targets, I've seen an example with a setIsDef(true) for such physically mapped register. Is there something missing in my code (register other...
2015 Nov 23
3
Qs about TwoOperandAliasConstraint and TIED_TO
in llvm-3.6.2.src 1. when I put this around one of my instruction definitions in my target "InstrInfo.td" file, let TwoOperandAliasConstraint = "$dst = $rs1" in { } I do not see any TIED_TO in the generated GenInstrInfo.inc file for the OperandInfo used by the instruction, the question is what am I doing wrong ? 2. I've noticed that TwoOperandAliasConstraint
2018 Apr 02
0
Mapping virtual registers to physical registers
...> >                 TII->loadRegFromStackSlot(*MBB, > >                                                 MI, destinationReg, > FrameIndex, > > > &CLP::FPUaOffsetClassRegClass, TRI); > > > The code after customInserter seems valid but the compilation later > hang-up in an infinite loop in procedure computeVirtRegs(); of pass > LiveIntervals::runOnMachineFunction. > > In other targets, I’ve seen an example with a setIsDef(true) for such > physically mapped register. Is there something missing in...
2014 Jul 02
2
[LLVMdev] Passing specific register for an Instruction in target description files.
...If you use this approach, you may run into issues if the scheduler decides to put two instructions that write to this register class in a row. In this case you will either need to implement spilling or the register allocator will run out of registers. The other way to solves this is to use the CustomInserter to force the instruction to use the register you want. -Tom > Cheers, > -Quentin > > > > > Currently I have seen that we can pass the name of the registers' group, and > > direct registers as an implicit operands (with Uses or Defs) but I want to > > pass s...
2014 Jun 20
3
[LLVMdev] Passing specific register for an Instruction in target description files.
Hi all, I want to generate an assembly instruction for my target using target description representation of the instruction. The problem is that I want to add direct register to be chose as an output register for my target. Does it possible to do with an instruction definition in TARGETInstrInfo.td file? May be someone could help with an example? Currently I have seen that we can pass the name
2018 Apr 03
1
Mapping virtual registers to physical registers
...> >                 TII->loadRegFromStackSlot(*MBB, > >                                                 MI, destinationReg, > FrameIndex, > > > &CLP::FPUaOffsetClassRegClass, TRI); > > > The code after customInserter seems valid but the compilation later > hang-up in an infinite loop in procedure computeVirtRegs(); of pass > LiveIntervals::runOnMachineFunction. > > In other targets, I’ve seen an example with a setIsDef(true) for such > physically mapped register. Is there something missing in...