search for: currmop

Hi, Regarding the mischeduler, I wonder // For loops that are acyclic path limited, aggressively schedule for // latency. This can result in very long dependence chains scheduled in // sequence, so once every cycle (when CurrMOps == 0), switch to normal // heuristics. if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() && tryLatency(TryCand, Cand, *Zone)) return; Is this an error in comment or code? The CurrMOps is 0 once per cycle, which means this is actually done once per cycle, in con...

...ll x86 instructions are modeled as a single micro-op, and SB can decode 4 // instructions per cycle. // FIXME: Identify instructions that aren't a single fused micro-op.    let IssueWidth = 4; , which also seem to indicate (1). What's more, I see that checkHazard() returns true if '(CurrMOps + uops > SchedModel->getIssueWidth())'. This means that the SU will be put in Pending instead of Available based on the number of microops it uses. To me this seems like an in-order decoding hazard check, since an OOO machine will rearrange the microops during execution, so there is...

...s a single micro-op, and SB can decode 4 > // instructions per cycle. > // FIXME: Identify instructions that aren't a single fused micro-op. > let IssueWidth = 4; > > , which also seem to indicate (1). > > What's more, I see that checkHazard() returns true if '(CurrMOps + uops > SchedModel->getIssueWidth())'. > This means that the SU will be put in Pending instead of Available based on the number of microops it uses. > To me this seems like an in-order decoding hazard check, since an OOO machine will rearrange the microops > during execution, s...