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...ion=0x5abb20 "virtual llvm::RecTy* llvm::UnOpInit::getFieldType(const std::string&) const") at assert.c:81 #3 0x000000000050ddc8 in llvm::UnOpInit::getFieldType (this=0x850f00, FieldName=...) at Record.cpp:633 #4 0x0000000000543f64 in llvm::TGParser::ParseValue (this=0x7fffffffd480, CurRec=0x8511d0, ItemType=0x851540) at TGParser.cpp:1342 #5 0x0000000000544574 in llvm::TGParser::ParseValueList (this=0x7fffffffd480, CurRec=0x8511d0, ArgsRec=0x8510d0, EltTy=0x0) at TGParser.cpp:1405 #6 0x000000000053e520 in llvm::TGParser::ParseSubClassReference (this=0x7fffffffd480, CurRec=0x8511d0,...

...20 "virtual llvm::RecTy* llvm::UnOpInit::getFieldType(const std::string&) const") at assert.c:81 > #3 0x000000000050ddc8 in llvm::UnOpInit::getFieldType (this=0x850f00, FieldName=...) at Record.cpp:633 > #4 0x0000000000543f64 in llvm::TGParser::ParseValue (this=0x7fffffffd480, CurRec=0x8511d0, ItemType=0x851540) at TGParser.cpp:1342 > #5 0x0000000000544574 in llvm::TGParser::ParseValueList (this=0x7fffffffd480, CurRec=0x8511d0, ArgsRec=0x8510d0, EltTy=0x0) at TGParser.cpp:1405 > #6 0x000000000053e520 in llvm::TGParser::ParseSubClassReference (this=0x7fffffffd480, CurRec...

...cTy* > llvm::UnOpInit::getFieldType(const std::string&) const") at assert.c:81 > > #3 0x000000000050ddc8 in llvm::UnOpInit::getFieldType (this=0x850f00, > FieldName=...) at Record.cpp:633 > > #4 0x0000000000543f64 in llvm::TGParser::ParseValue > (this=0x7fffffffd480, CurRec=0x8511d0, ItemType=0x851540) at > TGParser.cpp:1342 > > #5 0x0000000000544574 in llvm::TGParser::ParseValueList > (this=0x7fffffffd480, CurRec=0x8511d0, ArgsRec=0x8510d0, EltTy=0x0) at > TGParser.cpp:1405 > > #6 0x000000000053e520 in llvm::TGParser::ParseSubClassReference &gt...

On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote: > > Currently, we rely on switch tables to transform between formats. However, > we would like to have a different mechanism to represent these relationships > instead of switch tables. I am thinking of modeling these relations in > HexagonInstrInfo.td file and use TableGen to generate a table with

...se); while (1) { // Check for error. if (SubClass.Rec == 0) return true; // Get the expanded definition prototypes and teach them about // the record values the current class to inherit has for (unsigned i = 0, e = NewRecDefs.size(); i != e; ++i) { Record *CurRec = NewRecDefs[i]; **** proposed changes -begin ***** if (SubClass.Rec->isSubClassOf("Relations")) { std::vector<Init*> InstrFormats(SubClass.Rec->getValues().size()); 1) Traverse thru all the records to see if CurRec's InstrFormat is same as the P...

Hi, I'm looking for some suggestions on a problem related to the Hexagon backend. Hexagon architecture allows instructions in various formats. For example, we have 3 variations of the add instruction as defined below: ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 = add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is true ADDrr_np :

Hello everyone, I bring to discussion the necessity/design of a new type of smart pointer. r215176 and r217791 rise the problem, D5443 <http://reviews.llvm.org/D5443> is devoted to the solution. r215176 applies several temporary ugly fixes of memory leaks in TGParser.cpp which would be great to be refactored using smart pointers. D5443 <http://reviews.llvm.org/D5443> demonstrates