search for: curdag

Dan Gohman wrote: > There certainly are wishlist items for TableGen and TableGen-based > instruction descriptions, though I don't know of an official list. > Offhand, > a few things that come to mind are the ability to handle nodes with > multiple results, Is there an official workaround, BTW? - Volodya

...d in Combine(BeforeLegalizeTypes) and should be optimized in Combine(AfterLegalizeTypes). But LegalizeTypes() did not change anything and Combine(AfterLegalizeTypes) was not called. Vector legalization that comes afterwards just scalarized the operation. SelectionDAGISel::CodeGenAndEmitDAG() .. CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); bool Changed; Changed = CurDAG->LegalizeTypes(); if (Changed) { CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); } The problem does not exist if the function is bigger and something was changed on LegalizeTypes() stage....

...ave entered a block"<<std::endl; static int numberOfBlocks=0; numberOfBlocks++; std::cout<<"-We are in Block:"<<numberOfBlocks<<std::endl; //FIRST OF ALL, LET US TRY NUMBERING THE NODES int in=0; for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),E = CurDAG->allnodes_end(); I != E; ++I) { I->setNodeId(in++); } //END NUMBERING THE NODES. //LET'S TRY WRITING A FILE std::ofstream myfile; std::string filename="DDGBLOCK"+convertInt(numberOfBlocks)+".txt"; myf...

...include a register copy so I know it's guaranteed to be loading from the correct register class in the end. I tried mocking this up using the following. (Base is what's returned as the Ax in the move expression above when the DAG is constructed due to SelectAddr().) SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); This actually generates valid, but horrible code: int deref(int *p) { return *p; } gives move.l a0, a3 -- a0 is a live in (first pointer arg) move.l (a3), d0 -- d0 is a live out (first int...

...tters - perhaps someone more knowledgeable could comment? > > Given that operand OpNo of Node needs to be a load, this is the code snippet I used: > > // Now we know which node to spill, perform the spill. > SDValue SpillVal = Node->getOperand(OpNo); > SDValue SpillSlot = CurDAG->CreateStackTemporary(SpillVal.getValueType()); > int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); > SDValue Chain = CurDAG->getStore(CurDAG->getEntryNode(), > SpillVal.getDebugLoc(), >...

...I have modified the SelectionDAGISel::CodeGenAndEmitDAG() function as follows void SelectionDAGISel::CodeGenAndEmitDAG() { std::string GroupName; //JOE'S EDITS START std::cout<<"Hello everybody Joe was here!"<<std::endl; for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),E = CurDAG->allnodes_end(); I != E; ++I) { std::cout<<"start"<<I->getOperationName(CurDAG)<<std::endl; } //JOE'S EDITS END ...and, for santity checking purposes, I've added similar code at the end... // Free the Sel...

...an immediate and, if it can't, produces a load: --------------------------------------------------------------------------------------- const Type *OpNTy = MVT::getTypeForValueType(MVT::i32); Constant *C = ConstantUInt::get(OpNTy, t); int alignment = 2; SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment); Arg = CurDAG->getLoad(MVT::i32, CurDAG->getEntryNode(), Addr, CurDAG->getSrcValue(NULL)); ---------------------------------------------------------------------------------------- This fails with the ass...

2008/2/15, Andreas Fredriksson <deplinenoise at gmail.com>: > > I tried mocking this up using the following. (Base is what's returned as > the Ax in the move expression above when the DAG is constructed due to > SelectAddr().) > > SDOperand chain = CurDAG->getCopyToReg(Base, M68K::A3, Base); > Base = CurDAG->getCopyFromReg(chain, M68K::A3, MVT::i32); > Replying to myself here. This worked a bit better :) const unsigned addressReg = RegMap->createVirtualRegister(&M68K::AR32RegClass); SDOperand chain = CurDAG->getC...

...resultReg; SDLoc dl = SDLoc(Node); SDValue id = Node->getOperand(0); EVT resultType = Node->getValueType(0); if(Subtarget->is64Bit()) { idReg = X86::RCX; resultReg = X86::RAX; } else { idReg = X86::ECX; resultReg = X86::EAX; } idRegValue = CurDAG->getRegister(idReg, resultType); SmallVector<SDValue, 8> Ops; SDValue setIdNode = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, idRegValue, id, SDValue()); SDValue rdmsrNode = SDValue(CurDAG->getMachineNode(X86::RDMSR, dl, MVT::Other, setIdNode), 0); SDValue resul...

...========================================================= --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (revision 72159) +++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (working copy) @@ -611,6 +611,36 @@ DOUT << "Optimized type-legalized selection DAG:\n"; DEBUG(CurDAG->dump()); } + + if (TimePassesIsEnabled) { + NamedRegionTimer T("Vector Legalization", GroupName); + Changed = CurDAG->LegalizeVectors(); + } else { + Changed = CurDAG->LegalizeVectors(); + } + + if (Changed) { + if (TimePassesIsEnabled) { +...

...t;< '\n'; } }; } @@ -678,12 +678,12 @@ // Codegen the basic block. #ifndef NDEBUG - DEBUG(errs() << "===== Instruction selection begins:\n"); + DEBUG(dbgs() << "===== Instruction selection begins:\n"); Indent = 0; #endif SelectRoot(*CurDAG); #ifndef NDEBUG - DEBUG(errs() << "===== Instruction selection ends:\n"); + DEBUG(dbgs() << "===== Instruction selection ends:\n"); #endif CurDAG->RemoveDeadNodes(); @@ -853,7 +853,7 @@ bool is64Bit = Subtarget->is64Bit(); DebugLoc dl = N.getDeb...

...> perhaps someone more knowledgeable could comment? > > Given that operand OpNo of Node needs to be a load, this is the code > snippet I used: > > // Now we know which node to spill, perform the spill. > SDValue SpillVal = Node->getOperand(OpNo); > SDValue SpillSlot = CurDAG->CreateStackTemporary(SpillVal.getValueType()); > int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); > SDValue Chain = CurDAG->getStore(CurDAG->getEntryNode(), > SpillVal.getDebugLoc(), >...

...return new (NodeAllocator.template Allocate<SDNodeT>()) SDNodeT(std::forward<ArgTypes>(Args)...); } */ char *exprStrChar = (char *)malloc(2048); strcpy(exprStrChar, "test... ..."); SDValue extSym = CurDAG->getTargetExternalSymbol( exprStrChar, MVT::i64); SDNode *extSymNode = extSym.getNode(); std::vector<SDValue> opsRes; opsRes.push_back(SDValue(vloadSpecial, 0)...

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->a...

...lizeTypes) and should be optimized in Combine(AfterLegalizeTypes). But LegalizeTypes() did not change anything and Combine(AfterLegalizeTypes) was not called. > Vector legalization that comes afterwards just scalarized the operation. > > SelectionDAGISel::CodeGenAndEmitDAG() > .. >   CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); > >   bool Changed; >   Changed = CurDAG->LegalizeTypes(); > >   if (Changed) { >      CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); >    } > > The problem does not exist if the function is bigger and something...

...========================================================= --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (revision 72159) +++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (working copy) @@ -611,6 +611,36 @@ DOUT << "Optimized type-legalized selection DAG:\n"; DEBUG(CurDAG->dump()); } + + if (TimePassesIsEnabled) { + NamedRegionTimer T("Vector Legalization", GroupName); + Changed = CurDAG->LegalizeVectors(); + } else { + Changed = CurDAG->LegalizeVectors(); + } + + if (Changed) { + if (TimePassesIsEnabled) { +...

...n register it fails the assertion `ResNo < NumValues && "Illegal result number!"'. More specifically I am doing something like: EVT ReturnValueVT = Node->getValueType(0) ; SDValue ChainIn = Node->getOperand(0); SDValue Zero = CurDAG->getCopyFromReg(ChainIn, DL, Mips::ZERO, MVT::i32); SDValue op0 = Node->getOperand(2); SDValue op1 = Node->getOperand(3); SDValue op2= Node->getOperand(4); SDValue op3 = Node->getOperand(5); SDValue Ops[]= { op0,...

...nd instead I just emit FrameIndex as immediate: bool MyBackendDAGToDAGISel::SelectAddrFI(SDValue &N, SDValue &R) { if (N.getOpcode() != ISD::FrameIndex) return false; MachineFrameInfo &MFI = MF->getFrameInfo(); int FX = cast<FrameIndexSDNode>(N)->getIndex(); R = CurDAG->getTargetFrameIndex(FX, MVT::i32); return true; } This way I end up with store %r1, [1] and handle it in my CPU emulator accordingly. So, instead of matching that FrameIndex in store, I really want to emit a load first and then use a register in the store instruction. Can you, please, adv...

...adapted it to my target: case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = N->getOperand(0); SDValue Op2 = N->getOperand(1); unsigned LoReg = R0, HiReg = R1; unsigned Opc = MULRdRr; SDValue InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, Op1, Op2), 0);...

On Sep 9, 2010, at 12:59 PM, Borja Ferrer wrote: > Hello, i've noticed a new possible missed optimization while testing more trivial code. > This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved. > > C code: > > typedef short t; > t foo(t a, t b) > { > t a4 = a*b; > return a4; > } >