search for: cur_level

...tic int > gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, > int *state, int load) > { > struct gk20a_pmu_dvfs_data *data = pmu->data; > struct nvkm_clk *clk = pmu->base.subdev.device->clk; > + struct nvkm_pstate *pstate = clk->pstate; > int cur_level, level; > > + if (!pstate) { > + *state = 0; > + return 1; > + } > + > /* For GK20A, the performance level is directly mapped to pstate */ > - level = cur_level = clk->pstate; > + level = cur_level = clk->pstate->pstate; > > if (load > data...

...; static int > gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, > int *state, int load) > { > struct gk20a_pmu_dvfs_data *data = pmu->data; > struct nvkm_clk *clk = pmu->base.subdev.device->clk; > + struct nvkm_pstate *pstate = clk->pstate; > int cur_level, level; > > + if (!pstate) { > + *state = 0; > + return 1; > + } > + > /* For GK20A, the performance level is directly mapped to pstate */ > - level = cur_level = clk->pstate; > + level = cur_level = clk->pstate->pstate; > > if (load > data-&gt...

...e = clk->pstate; - return 0; -} - -static int gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, int *state, int load) { struct gk20a_pmu_dvfs_data *data = pmu->data; struct nvkm_clk *clk = pmu->base.subdev.device->clk; + struct nvkm_pstate *pstate = clk->pstate; int cur_level, level; + if (!pstate) { + *state = 0; + return 1; + } + /* For GK20A, the performance level is directly mapped to pstate */ - level = cur_level = clk->pstate; + level = cur_level = clk->pstate->pstate; if (load > data->p_load_max) { level = min(clk->state_nr - 1, lev...

...gt;> int *state, int load) >> { >> struct gk20a_pmu_dvfs_data *data = pmu->data; >> struct nvkm_clk *clk = pmu->base.subdev.device->clk; >> + struct nvkm_pstate *pstate = clk->pstate; >> int cur_level, level; >> + if (!pstate) { >> + *state = 0; >> + return 1; >> + } >> + >> /* For GK20A, the performance level is directly mapped to pstate >> */ >> - level = cur_level = clk->pstate; >> +...

...k; - - *state = clk->pstate; -} - static int gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, int *state, int load) { struct gk20a_pmu_dvfs_data *data = pmu->data; struct nvkm_clk *clk = pmu->base.subdev.device->clk; + struct nvkm_pstate *pstate = clk->pstate; int cur_level, level; + if (!pstate) { + *state = 0; + return 1; + } + /* For GK20A, the performance level is directly mapped to pstate */ - level = cur_level = clk->pstate; + level = cur_level = clk->pstate->pstate; if (load > data->p_load_max) { level = min(clk->state_nr - 1, lev...

...k; - - *state = clk->pstate; -} - static int gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu, int *state, int load) { struct gk20a_pmu_dvfs_data *data = pmu->data; struct nvkm_clk *clk = pmu->base.subdev.device->clk; + struct nvkm_pstate *pstate = clk->pstate; int cur_level, level; + if (!pstate) { + *state = 0; + return 1; + } + /* For GK20A, the performance level is directly mapped to pstate */ - level = cur_level = clk->pstate; + level = cur_level = clk->pstate->pstate; if (load > data->p_load_max) { level = min(clk->state_nr - 1, lev...

...k->pstate; > + return 0; > +} > + > +static int > +gk20a_dvfs_get_target_state(struct nouveau_dvfs *dvfs, int *state, int load) > +{ > + struct nouveau_dvfs_data *data = dvfs->data; > + struct nouveau_clock *clk = nouveau_clock(dvfs); > + int cur_level, level; > + > + /* For GK20A, the performance level is directly mapped to pstate */ > + level = cur_level = clk->pstate; > + > + if (load > data->p_load_max) { > + level = min(clk->state_nr - 1, level + (clk->state_nr / 3)); > +...

...gt; +static int >>> +gk20a_dvfs_get_target_state(struct nouveau_dvfs *dvfs, int *state, int >>> load) >>> +{ >>> + struct nouveau_dvfs_data *data = dvfs->data; >>> + struct nouveau_clock *clk = nouveau_clock(dvfs); >>> + int cur_level, level; >>> + >>> + /* For GK20A, the performance level is directly mapped to pstate >>> */ >>> + level = cur_level = clk->pstate; >>> + >>> + if (load > data->p_load_max) { >>> + level = min(clk...

Hi, This is a try to have some simple DVFS (Dynamic Voltage and Frequency Scaling) support for GK20A. Instead of relying on other existing frequency scaling framework, we create a simple subdev in Nouveau for the same purpose. That's because we don't want to make the DVFS implementation for GK20A far more than enough in the beginning and hinder the implementation for dGPU in the future.

...+{ + struct nouveau_clock *clk = nouveau_clock(dvfs); + + *state = clk->pstate; + return 0; +} + +static int +gk20a_dvfs_get_target_state(struct nouveau_dvfs *dvfs, int *state, int load) +{ + struct nouveau_dvfs_data *data = dvfs->data; + struct nouveau_clock *clk = nouveau_clock(dvfs); + int cur_level, level; + + /* For GK20A, the performance level is directly mapped to pstate */ + level = cur_level = clk->pstate; + + if (load > data->p_load_max) { + level = min(clk->state_nr - 1, level + (clk->state_nr / 3)); + } else { + level += ((load - data->p_load_target) * 10 / + da...

...n 0; >> +} >> + >> +static int >> +gk20a_dvfs_get_target_state(struct nouveau_dvfs *dvfs, int *state, int load) >> +{ >> + struct nouveau_dvfs_data *data = dvfs->data; >> + struct nouveau_clock *clk = nouveau_clock(dvfs); >> + int cur_level, level; >> + >> + /* For GK20A, the performance level is directly mapped to pstate */ >> + level = cur_level = clk->pstate; >> + >> + if (load > data->p_load_max) { >> + level = min(clk->state_nr - 1, level + (clk->s...

...>> +gk20a_dvfs_get_target_state(struct nouveau_dvfs *dvfs, int *state, int >>>> load) >>>> +{ >>>> + struct nouveau_dvfs_data *data = dvfs->data; >>>> + struct nouveau_clock *clk = nouveau_clock(dvfs); >>>> + int cur_level, level; >>>> + >>>> + /* For GK20A, the performance level is directly mapped to pstate >>>> */ >>>> + level = cur_level = clk->pstate; >>>> + >>>> + if (load > data->p_load_max) { >>>> +...

There might be some callers of nouveau_clock_astate(), and they are from inetrrupt context. So we must ensure that this function can be atomic in that condition. This patch adds one parameter which is subsequently passed to nouveau_pstate_calc(). Therefore we can choose whether we want to wait for the pstate work's completion or not. Signed-off-by: Vince Hsu <vinceh at nvidia.com> ---

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of changing the clock state due to temperature changes and dynamic reclocking. v2: remove commits

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. racy reclocking while GPU is suspending and leading to hangs Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of changing the clock state due to

This series addresses various issues inside the reclocking code: 1. after resume the set clocks are reset 2. reclocking not possible while GPU is suspended 3. nouveau always does full reclocks even if only a change of the voltage is required Some of the patches were part of the bigger reclocking series I sent months ago, some things have changed though. This is also preparation work of

Adds Nouveau controlled thermal throttling for Kepler+ GPUs. With this I feel safe enough to add support for Maxwell2 reclocking later on (still hidden behind a switch, but we can be fairly sure to not overheat hardware if a user isn't carefull enough) Contains all patches from my clk update series, but I thought it makes sense to include those in this series as well for completness. Please

Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html Basically big cleanup, reordering, simplifications and some renaming to make the code easier to read and to review. I also moved some bugfixes to the front so they can be merged prior the other patches. There was also a bug related to the therm daemon triggering a pstate change leading to PMU lockups,

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add

This is an updated series for the old clocking improvement one. I think I got everything needed in place and also a simple update mechanism for updating the cstates/voltage on temperature changes. If anything is unclear how I REed or got the information, please leave a note so that I can provide additional information in the commits. Besides that I think we are pretty close now and only some