search for: ctpop

Hi, Following is excerpted from http://llvm.org/releases/3.1/docs/LangRef.html#int_ctpop. How come the return type needs to be consistent with parameter type? i64/i128 seems to be overkill, and i8, i16 are inconvenient. ----------------------------------- declare i8 @llvm.ctpop.i8(i8 <src>) declare i16 @llvm.ctpop.i16(i16 <src>) declare i32 @llvm.ctpop.i32(i32...

Quick question. The 'ISD::CTPOP' node allows a target to lower the counting of ones in a word to a single instruction. Our target also has an instruction for counting the zeroes in a word. Does CTPOP support counting of zeroes as well as ones instead of doing either "CTPOP(INVERT(operand))" or "N-bits - CTPOP...

On 1/18/2018 12:57 AM, ORiordan, Martin via llvm-dev wrote: > Quick question. The 'ISD::CTPOP' node allows a target to lower the counting of ones in a word to a single instruction. Our target also has an instruction for counting the zeroes in a word. Does CTPOP support counting of zeroes as well as ones instead of doing either "CTPOP(INVERT(operand))" or "N-bits - CTPOP...

Hello, is it correct, that the "llvm.ctpop" Hamming weight intrinsic is currently (LLVM 2.2) implemented in Line 254 in lib/CodeGen/IntrinsicLowering.cpp /// LowerCTPOP - Emit the code to lower ctpop of V before the specified /// instruction IP. static Value *LowerCTPOP(Value *V, Instruction *IP) { assert(V->getType()->isIn...

Hello. Could you please tell me why am I not able to recognize (with LLVM built from the SVN code in Apr 25, 2018) the LLVM IR intrinsic ctpop (described at https://llvm.org/docs/LangRef.html#llvm-ctpop-intrinsic) in the following program: int PopCnt_Simple(int x) { int numBits = 0; int i; //for (i = 0; i < 32; i++) { for (i = 0; x != 0; i++) { if (x & 1)...

...s already been updated to generate the new intrinsic names. Other front-ends will start seeing warnings about the names of intrinsics that need to be upgraded in the front end. Here are the intrinsics that need to be changed: llvm.bswap -> llvm.bswap.i16, llvm.bswap.i32, llvm.bswap.i64 llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt...

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

...RTLIB::SRA_I16, RTLIB::SRA_I16, RTLIB::SRA_I32, RTLIB::SRA_I64, RTLIB::SRA_I128)); I think this is a BUG by omission of necessary switch cases. Similarly, the following ISD codes ISD::CTTZ, ISD::CTLZ, ISD::CTPOP do not define any Library calls, despite LLVM being able to fully expand them into rather large code for targets that do not natively implement them. I regard this also as an omission/bug, because not all targets would benefit from the custom expansion of these ISD codes, which as said can get unne...

Hi Chris, > Of interest may be this thesis. It talks about converting alpha code > to LLVM (among other things): > http://llvm.org/pubs/2004-05-JoshiMSThesis.html Thanks, it was of interest. I didn't spot its relevance from the title. Cheers, Ralph.

...a lot of cases. So I’m not eager to add partial support just for out-of-tree targets. > > Marking CTLZ_ZERO_UNDEF as “LibCall” was implemented in https://reviews.llvm.org/D47917 <https://reviews.llvm.org/D47917> . Probably straightforward to extend that to cover CTTZ_ZERO_UNDEF and CTPOP. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev > Sent: Monday, June 10, 2019 8:31 AM > To: llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] [llvm-dev] Bug: Library functions for ISD::SRA, ISD::SHL, an...

...nstruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–like multiplication or ctpop/ctlz/cttz?)</p><p>If the CPU does not have a dedication clmul operation, it can be lowered to regular multiplication, by using holes to avoid carrys.</p><p>==Where is clmul used?==</p><p>While somewhat specialized, the RISC-V manual documents many uses: [2]</p...

...nstruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–like multiplication or ctpop/ctlz/cttz?) >> >>  If the CPU does not have a dedication clmul operation, it can be lowered to regular multiplication, by using holes to avoid carrys. >> >>  ==Where is clmul used?== >> >>  While somewhat specialized, the RISC-V manual documents many uses: [2] &g...

...a lot of cases. So I’m not eager to add partial support just for out-of-tree targets. > > Marking CTLZ_ZERO_UNDEF as “LibCall” was implemented in https://reviews.llvm.org/D47917 <https://reviews.llvm.org/D47917> . Probably straightforward to extend that to cover CTTZ_ZERO_UNDEF and CTPOP. > > -Eli > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org <mailto:llvm-dev-bounces at lists.llvm.org>> On Behalf Of Joan Lluch via llvm-dev > Sent: Monday, June 10, 2019 8:31 AM > To: llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm....

...into multiple IR instructions? As noted here, it's unlikely for rotate. If it is possible, then adding folds to instcombine for this intrinsic isn't hard. Are any other passes affected? For reference, these are the current target-independent bit-manipulation intrinsics - bswap, bitreverse, ctpop, ctlz, cttz: http://llvm.org/docs/LangRef.html#bit-manipulation-intrinsics The LLVM cost for the proposed rotate intrinsic should be in the same range as those? Note that we would not just be adding code to support an intrinsic. There are already ~200 lines of DAG matching code for rotate, so we a...

...case ISD::FSUB: + case ISD::FMUL: + case ISD::FDIV: + case ISD::FREM: + case ISD::AND: + case ISD::OR: + case ISD::XOR: + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: + case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: + case ISD::SELECT: + case ISD::SELECT_CC: + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: + case ISD::FNEG: + case ISD::FABS: + case ISD::FSQRT: + case ISD::FSIN: + case ISD::FCOS: + case ISD::FPOWI: + case ISD...

On 2018-05-16 00:34, Sanjay Patel via llvm-dev wrote: > Vectorization goes overboard because the throughput cost model used by > the > vectorizers doesn't match the 6 IR instructions that correspond to 1 > x86 > rotate instruction. Instead, we have: > > [...] > > The broken cost model also affects unrolling and inlining. Size costs > are > overestimated

...nstruction. It takes two integer operands of the same width, and returns an integer with twice the width of the operands. (Is there a good reason to make these the same width, as all the other operations do even when it doesn’t really make sense for the mathematical operation–like multiplication or ctpop/ctlz/cttz?) > > If the CPU does not have a dedication clmul operation, it can be lowered to regular multiplication, by using holes to avoid carrys. > > ==Where is clmul used?== > > While somewhat specialized, the RISC-V manual documents many uses: [2] > > The classic applica...

...ones contributed patches to improve our doxygen output. 32. Misha renamed the llvm 'extract' tool to 'llvm-extract' (makes sense!) 33. Justin Wick contributed support for a new llvm.prefetch intrinsic. llvm-gcc now compiles __builtin_prefetch to it. 34. Andrew added llvm.ctpop,llvm.cttz and llvm.ctlz intrinsics. llvm-gcc now codegens __builtin_popcount, etc to these intrinsics. 35. Duraid contributed patches to build LLVM on HP-UX with the GNU toolchain. He also got it working with aCC, but it requires several work-arounds for the (rather old) STL i...

...Some front-end pieces will land in LLVM 2.1 though. 6. Anton and Lauro implemented support for 'protected visibility' in ELF. 7. Anton implemented support for ELF symbol aliases. 8. Reid contributed support for 'polymorphic intrinsics', allowing things like llvm.ctpop to work on arbitrary width integers. llvm-gcc Improvements: 9. Duncan Sands contributed many enhancements to llvm-gcc, some of which are language independent and others that are aimed towards better Ada support. He made improvements to NON_LVALUE_EXPR, arrays with non-zero base...

...case ISD::FSUB: + case ISD::FMUL: + case ISD::FDIV: + case ISD::FREM: + case ISD::AND: + case ISD::OR: + case ISD::XOR: + case ISD::SHL: + case ISD::SRA: + case ISD::SRL: + case ISD::ROTL: + case ISD::ROTR: + case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: + case ISD::SELECT: + case ISD::SELECT_CC: + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + case ISD::TRUNCATE: + case ISD::SIGN_EXTEND: + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: + case ISD::FNEG: + case IS...