Displaying 6 results from an estimated 6 matches for "csed".
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2009 Aug 17
2
[LLVMdev] canonicalizing types for vector operations
I committed a change to fix pr4731 yesterday but after thinking about
it some more, I'd like to get other opinions about this. Chris and I
talked last week about the need to canonicalize the types used for
Neon vector shuffles so that they get CSEd. I guess this was an issue
that came up for SSE.
For pr4731, I changed llvm-gcc to canonicalize a bitwise vector
operation to use i32 elements. For these operations, the type doesn't
matter since the vector are treated as a bunch of bits. I was
thinking that we should do the canonic...
2009 Aug 09
2
[LLVMdev] proposal to add MVT::vAny type
...2009, at 8:37 AM, Chris Lattner wrote:
> I really do think that bitcast is the right way to go here. I ran
> into a couple of similar problems when bringing up the altivec port.
> For example, at one time we'd get "all zero vectors" of different
> MVTs, which would not be CSEd.
>
> The fix for this was to be really disciplined about what types to make
> things in, and use bitcasts to convert the types when appropriate.
> For example, the all zeros vector is now only created as a <4 x i32>
> (IIRC) and bitcasted to the desired type.
Yes, I used that...
2009 Aug 09
0
[LLVMdev] proposal to add MVT::vAny type
...for the load/store
> lane operations.
Hi Bob,
I really do think that bitcast is the right way to go here. I ran
into a couple of similar problems when bringing up the altivec port.
For example, at one time we'd get "all zero vectors" of different
MVTs, which would not be CSEd.
The fix for this was to be really disciplined about what types to make
things in, and use bitcasts to convert the types when appropriate.
For example, the all zeros vector is now only created as a <4 x i32>
(IIRC) and bitcasted to the desired type. If this is impacting
intrinsics,...
2015 Sep 29
3
Duplicating node in SelectionDAG?
It appears that it's impossible to duplicate a node in the dag. For
example, there is some code:
b = a * a; // a is a global int
A LD node is generated for A and it goes into both Operand 0 and 1 of the
MUL node. The issue is I'm trying to match a pattern of:
set dstReg:$dstD (OpNode (srcAType (load addr32:$srcA)), (srcBType (load
addr32:$srcB)))
so basically a mem, mem, reg
2009 Aug 17
0
[LLVMdev] canonicalizing types for vector operations
...at 7:15 AM, Bob Wilson wrote:
> I committed a change to fix pr4731 yesterday but after thinking about
> it some more, I'd like to get other opinions about this. Chris and I
> talked last week about the need to canonicalize the types used for
> Neon vector shuffles so that they get CSEd. I guess this was an issue
> that came up for SSE.
>
> For pr4731, I changed llvm-gcc to canonicalize a bitwise vector
> operation to use i32 elements. For these operations, the type doesn't
> matter since the vector are treated as a bunch of bits. I was
> thinking that we...
2009 Aug 09
4
[LLVMdev] proposal to add MVT::vAny type
The ARM Neon load, store and shuffle operations that I've been
implementing recently with LLVM intrinsics do not care about the
distinction between vectors with i32 and f32 elements -- only the size
matters. But, because we have only MVT::fAny and MVT::iAny types,
I've been having to define separate intrinsics for the operations with
floating-point vector elements. It