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----- Original Message ----- > From: "Jakob Stoklund Olesen" <stoklund at 2pi.dk> > To: "Hal Finkel" <hfinkel at anl.gov> > Cc: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, "Akira Hatanaka" <ahatanak at gmail.com> > Sent: Saturday, April 6, 2013 11:56:28 AM > Subject: Re: [LLVMdev] [PATCH]

...that I've added). However, despite all > of that, I can't seem to get RA to split the following: > > 1 BB#0: derived from LLVM BB %entry > 2 Live Ins: %X3 > 3 %vreg15<def> = COPY %X3; G8RC:%vreg15 > 4 %vreg4<def> = CMPLDI %vreg15, 0; CRRC:%vreg4 G8RC:%vreg15 > 5 %vreg11:sub_32<def,read-undef> = LI 0; G8RC:%vreg11 > 6 BCC 68, %vreg4, <BB#1>; CRRC:%vreg4 > 7 Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) > BB#1(0x50000000 / 0x80000000 = 62.50%) > 8 > 9 BB...

...isting and experimental ones that I've added). However, despite all of that, I can't seem to get RA to split the following: 1 BB#0: derived from LLVM BB %entry 2 Live Ins: %X3 3 %vreg15<def> = COPY %X3; G8RC:%vreg15 4 %vreg4<def> = CMPLDI %vreg15, 0; CRRC:%vreg4 G8RC:%vreg15 5 %vreg11:sub_32<def,read-undef> = LI 0; G8RC:%vreg11 6 BCC 68, %vreg4, <BB#1>; CRRC:%vreg4 7 Successors according to CFG: BB#4(0x30000000 / 0x80000000 = 37.50%) BB#1(0x50000000 / 0x80000000 = 62.50%) 8 9 BB#4: 10 Predecessors accor...

...; up being more complicated, but that, perhaps, is a separate issue. [To >> be clear, I am not advocating for (or against) this solution even if it >> would work for you]. > > Ok, thanks for the pointer, I'll go read in the PPC bits. I see that PPC has its condition registers CRRC as i32, and that PPC also has general purpose i32 registers GPRC, so the situation is slightly different than on Hexagon, where there are no general purpose registers of the same size as the predicate registers: i8. So on PPC it is "safe" to promote from i1 to i32 and to "allow conf...

...more complicated, but that, perhaps, is a separate issue. [To >>> be clear, I am not advocating for (or against) this solution even if it >>> would work for you]. >> Ok, thanks for the pointer, I'll go read in the PPC bits. > I see that PPC has its condition registers CRRC as i32, and that PPC > also has general purpose i32 registers GPRC, so the situation is slightly > different than on Hexagon, where there are no general purpose registers > of the same size as the predicate registers: i8. > > So on PPC it is "safe" to promote from i1 to i32...

..., but that, perhaps, is a separate issue. [To >>>> be clear, I am not advocating for (or against) this solution even if it >>>> would work for you]. >>> Ok, thanks for the pointer, I'll go read in the PPC bits. >> I see that PPC has its condition registers CRRC as i32, and that PPC >> also has general purpose i32 registers GPRC, so the situation is slightly >> different than on Hexagon, where there are no general purpose registers >> of the same size as the predicate registers: i8. >> >> So on PPC it is "safe" to pr...

On Thu, May 24, 2012 at 5:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Sebastian, > > First, it might be useful to look at what is done in the PowerPC > backend. PPC also has condition registers that are larger than the > 1-bit conditional results, and it defines 1-bit subregisters in > addition to the larger condition registers. The spill-restore code ends > up being

...aps, is a separate issue. [To >>>>> be clear, I am not advocating for (or against) this solution even if it >>>>> would work for you]. >>>> Ok, thanks for the pointer, I'll go read in the PPC bits. >>> I see that PPC has its condition registers CRRC as i32, and that PPC >>> also has general purpose i32 registers GPRC, so the situation is slightly >>> different than on Hexagon, where there are no general purpose registers >>> of the same size as the predicate registers: i8. >>> >>> So on PPC it is &q...

Sebastian, First, it might be useful to look at what is done in the PowerPC backend. PPC also has condition registers that are larger than the 1-bit conditional results, and it defines 1-bit subregisters in addition to the larger condition registers. The spill-restore code ends up being more complicated, but that, perhaps, is a separate issue. [To be clear, I am not advocating for (or against)