search for: crowdsupply

Displaying 13 results from an estimated 13 matches for "crowdsupply".

2019 Feb 01
2
[RFC] Vector Predication
--- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay <programmerjake at gmail.com> wrote: > > We're in-progress designing a RISC-V extension (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) that would have variable-length vectors of short vecto...
2019 Feb 01
3
[RFC] Vector Predication
On Fri, Feb 1, 2019 at 1:19 AM Bruce Hoult <brucehoult at sifive.com> wrote: > On Thu, Jan 31, 2019 at 11:53 PM Luke Kenneth Casson Leighton via > llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > --- > > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 > > > > On Thu, Jan 31, 2019 at 10:22 PM Jacob Lifshay <programmerjake at gmail.com> > wrote: > > > > > > We're in-progress designing a RISC-V extension ( > http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) >...
2019 Oct 02
2
Adding support for vscale
On Wed, 2 Oct 2019 at 05:09, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote: > > My general feeling on this then is that both RVV and SV should avoid using > vscale. > > In the case of RVV, MVL is a hardware defined constant that is never > *intended* to be known by applications. There's no published detection > mechanism. Loops are supposed to be designed
2019 Feb 01
3
[RFC] Vector Predication
Hi, On 1/31/19 11:20 PM, Jacob Lifshay wrote: > We're in-progress designing a RISC-V extension > (http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-January/000433.html) > that would have variable-length vectors of short vectors (1 to 4): > <VL x <4 x float>> > where each predicate bit masks out a whole short vector. We're using > this extension
2019 Feb 04
4
[RFC] Vector Predication
...L. That is the mask has a minimum element count of %L * mask sub-vector length, the data has a minimum element count of %L * data sub-vector length. - Simon > > Or, is that just a runtime error. > > L. > > > -- > --- > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 > -- Simon Moll Researcher / PhD Student Compiler Design Lab (Prof. Hack) Saarland University, Computer Science Building E1.3, Room 4.31 Tel. +49 (0)681 302-57521 : moll at cs.uni-saarland.de Fax. +49 (0)681 302-3065 : http://compilers.cs.uni-saarland.de/people/moll ------------...
2019 Sep 30
2
Adding support for vscale
I've posted two patches on Phabricator to add support for VScale in LLVM. A brief recap on `vscale`: The scalable vector type in LLVM IR is defined as `<vscale x n x m>`, to create types such as `<vscale x 16 x i8>` for a scalable vector with at least 16 bytes. In the definition of the scalable type, `vscale` is specified as a positive constant of type integer that will only be
2019 Sep 30
3
Adding support for vscale
...where in SV you get exactly what is requested and if overallocated an illegal instruction is raised. > > > > > [1] https://reviews.llvm.org/D68202 > > [2] https://reviews.llvm.org/D68203 > > Jacob Lifshay > -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20191001/222d6846/attachment.html>
2020 Jan 30
3
RFC: Switching from Bugzilla to Github Issues
On Thu, Jan 30, 2020, 10:22 Tom Stellard via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > I want to restart this discussion. There seemed to be support for this, > but we got held up trying to decide on the appropriate set of tags to > use to classify issues. > > I propose that we move forward with this proposal and disable creation of > new bugs in
2019 Feb 05
4
[RFC] Vector Predication
On 2/5/19 1:27 AM, Philip Reames via llvm-dev wrote: > > On 1/31/19 4:57 PM, Bruce Hoult wrote: >> On Thu, Jan 31, 2019 at 4:05 PM Philip Reames via llvm-dev >> <llvm-dev at lists.llvm.org> wrote: >>> Do such architectures frequently have arithmetic operations on the >>> mask registers?  (i.e. can I reasonable compute a conservative >>> length
2019 Jan 31
6
[RFC] Vector Predication
Hi, There is now an RFC for a roadmap to native vector predication support in LLVM and a prototype implementation:   https://reviews.llvm.org/D57504 The prototype demonstrates: -  Predicated vector intrinsics with an explicit mask and vector length parameter on IR level. -  First-class predicated SDNodes on ISel level. Mask and vector length are value operands. -  An incremental strategy
2019 Feb 08
5
[RFC] Vector Predication
On Thu, Feb 7, 2019, 09:21 Simon Moll <moll at cs.uni-saarland.de> wrote: > > On 2/7/19 6:08 PM, David Greene wrote: > > Jacob Lifshay <programmerjake at gmail.com> writes: > > > >> So it would be handy for the vector length on evl intrinsics to be in > >> units of the mask length so we don't have to pattern match a division > >> in the
2019 Oct 01
2
Adding support for vscale
Hi Luke, > was it intentional to leave out both jacob and myself? > [...] > if that was a misunderstanding or an oversight i apologise for raising it. It was definitely not my intention to be non-inclusive, my apologies if that seemed the case! > can i therefore recommend a change, here: > [...] > "This patch adds vscale as a symbolic constant to the IR, similar to >
2018 Aug 06
2
vectorisation, risc-v
...ard fork would be just insane and hugely counterproductive), so in particular regard to (4) documentation, guidelines and recommendations likely to result in the upstreaming process going smoothly also greatly appreciated. Many thanks, L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68 -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180806/9557a4a9/attachment.html>