search for: crossbars

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2018 Feb 05
0
[PATCH 3/3] drm/nouveau/pci: SOR crossbar quirk for 10b0:1b81
On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link 'G' (outp index 7) causes failures: [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 61c880 [ IBUS ] [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 [ 8.716668] nouveau 0000:01:00.0: DRM: base-0: timeout [ 10.716679] nouveau 0000:01:00.0: DRM: base-1: timeout [ 63.511862] nouveau
2018 Feb 05
0
[PATCH 3/3] drm/nouveau/pci: SOR crossbar quirk for 10b0:1b81
On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: > On 5 February 2018 at 11:22, Danilo Krummrich > <danilokrummrich at dk-develop.de> wrote: >> On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link >> 'G' (outp index 7) causes failures: >> >> [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at
2018 Feb 05
0
[PATCH 2/3] drm/nouveau/disp: quirk for SOR crossbar routing
With DCB 4.1 implemented by VBIOS since GM20x GPUs, SOR crossbar routing should be possible, such that any SOR sublink can drive any macro link. Unfortunately, there's at least one card where some SOR sublinks being connected to a particular macro link are causing failures. To work around this issue, supply a quirk for such cards which prevents a dynamic mapping of SOR sublink and macro link
2018 Feb 05
0
[PATCH v2 2/3] drm/nouveau/disp: quirk for SOR crossbar routing
With DCB 4.1 implemented by VBIOS since GM20x GPUs, SOR crossbar routing should be possible, such that any SOR sublink can drive any macro link. Unfortunately, there's at least one card where some SOR sublinks being connected to a particular macro link are causing failures. To work around this issue, supply a quirk for such cards which prevents a dynamic mapping of SOR sublink and macro link
2018 Feb 05
0
[PATCH 3/3] drm/nouveau/pci: SOR crossbar quirk for 10b0:1b81
On Mon, Feb 5, 2018 at 12:19 PM, Danilo Krummrich <danilokrummrich at dk-develop.de> wrote: > On 2018-02-05 02:39, Ben Skeggs wrote: >> >> On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: >>> >>> On 5 February 2018 at 11:22, Danilo Krummrich >>> <danilokrummrich at dk-develop.de> wrote: >>>>
2018 Feb 05
2
[PATCH 3/3] drm/nouveau/pci: SOR crossbar quirk for 10b0:1b81
On 5 February 2018 at 11:22, Danilo Krummrich <danilokrummrich at dk-develop.de> wrote: > On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link > 'G' (outp index 7) causes failures: > > [ 6.712111] nouveau 0000:01:00.0: bus: MMIO read of 00000000 FAULT at 61c880 [ IBUS ] > [ 6.724888] nouveau 0000:01:00.0: disp: intr24 80000000 > [ 8.716668]
2009 Sep 14
1
ggplot, ribbon not showing up properly
Hi, I'm trying to plot a longitudinal data set, using ggplot and adding some summary info (eg. mean, 1 sd bounds) using geom=ribbon. The summary info is based on a subset of the original data (eg. less an outlier). But I'm having trouble getting the ribbons to show up correctly. It's probably something obvious that I'm missing as a novice at ggplot2, and any help is much
2018 Feb 05
2
[PATCH 3/3] drm/nouveau/pci: SOR crossbar quirk for 10b0:1b81
On 2018-02-05 02:39, Ben Skeggs wrote: > On 5 February 2018 at 11:37, Ben Skeggs <skeggsb at gmail.com> wrote: >> On 5 February 2018 at 11:22, Danilo Krummrich >> <danilokrummrich at dk-develop.de> wrote: >>> On Gainward GTX 1070 routing any other SOR than SOR-1 to macro link >>> 'G' (outp index 7) causes failures: >>> >>> [
2014 Dec 14
1
DCB 4.1 spec update
On Sat, Dec 13, 2014 at 6:42 PM, Andy Ritger <aritger at nvidia.com> wrote: > On Wed, Dec 10, 2014 at 07:46:16AM +1000, Ben Skeggs wrote: >> On Wed, Dec 10, 2014 at 7:36 AM, Ben Skeggs <skeggsb at gmail.com> wrote: >> > On Wed, Dec 10, 2014 at 4:26 AM, Andy Ritger <aritger at nvidia.com> wrote: >> >> Hi, >> > Hey Andy, >> > >>
2008 Jun 14
1
Another name for EtherStub...
How about Virtual Network Crossbar or VNX for short. Darren
2014 Dec 09
2
DCB 4.1 spec update
On Wed, Dec 10, 2014 at 7:36 AM, Ben Skeggs <skeggsb at gmail.com> wrote: > On Wed, Dec 10, 2014 at 4:26 AM, Andy Ritger <aritger at nvidia.com> wrote: >> Hi, > Hey Andy, > >> >> The VBIOS on GM20x GPUs uses a slightly updated version of the DCB. >> I've posted an updated DCB spec here: >> >>
2014 Dec 13
0
DCB 4.1 spec update
On Wed, Dec 10, 2014 at 07:46:16AM +1000, Ben Skeggs wrote: > On Wed, Dec 10, 2014 at 7:36 AM, Ben Skeggs <skeggsb at gmail.com> wrote: > > On Wed, Dec 10, 2014 at 4:26 AM, Andy Ritger <aritger at nvidia.com> wrote: > >> Hi, > > Hey Andy, > > > >> > >> The VBIOS on GM20x GPUs uses a slightly updated version of the DCB. > >>
2008 Mar 26
2
Avantfax installation on Debian
Hi, I am having difficulty running Avantfax on Debian. When I try to launch the web UI, I get a whole page of PHP codes. It looks like my apache is not recognizing the PHP file. However, I am able to run phpmyadmin no problem which proves that apache2 is working with PHP. Any idea? Thanks, Pete -------------- next part -------------- An HTML attachment was scrubbed... URL:
2018 Feb 05
3
[PATCH 1/3] drm/nouveau/pci: PCI IDs for pascal architecture
Taken from NVIDIA binary driver (Linux 64-bit, revision 390.25) from README.txt. Signed-off-by: Danilo Krummrich <danilokrummrich at dk-develop.de> --- drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index
2007 Aug 28
9
Fax Problems with SpanDSP
....com/login/mrd.asp?CategoryID=120 http://www.shamrock.de/ I've got black bars over the pages. In Tobit some content is Ok, other is covered by the black bars. Anyone else has simliar problems? I talked to Tobit and they said there should be an option somewhere in SpanDSP to disable Fax header crossbars. But I found none. Can anybody help me with this issue. Please no "switch to Hylafax" mails, because I'm very happy with SpanDSP, it integrates nicely and works most time. Thank you, Regards Christian Peter
2018 Feb 05
2
[PATCH 0/1] drm/nouveau/disp: prefer identity-mapped route of SOR <-> macro link
Hi Ben, still _assuming_ it's an issue of the card I thought about why it works with the NVIDIA binary driver. And I can image they're just trying to do an identity-mapping first and if that doesn't work (e.g. the particular SOR is already in use by another macro link) they just pick the next suitable one. So the case would be that the NVIDIA binary driver always assignes the only
2018 Feb 05
2
[PATCH v2 1/3] drm/nouveau/pci: PCI IDs for pascal architecture
Taken from NVIDIA binary driver (Linux 64-bit, revision 390.25) from README.txt. Signed-off-by: Danilo Krummrich <danilokrummrich at dk-develop.de> --- drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index
2000 Oct 01
1
barplots with standard deviation
Hello! I'd like to print certain kinds of diagrams with R. They should look like barplots with besides=TRUE, but also have the variance or standard deviation on every bar so that one could better compare the bars. How could I apply this? thanks for your help Raoul -.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.- r-help mailing list -- Read
2005 Feb 25
1
Re: Asterisk-Users Digest, Vol 7, Issue 304
Daniel Nystrom wrote > It seems like the Radio discussions is closing in on something I was > interested in. > How about controlling 30 2-way radios via E1 and 30-channel "Mux" > (channel bank?) with E&M signalling? > I think the Mux uses CAS and each channel has Audio out, PTT, Audio > IN, Busy. 6-wire connection i guess? > That should be a really nice setup
2005 Sep 08
2
maximum cpus/cores in CentOS 4.1
What is the maximum number of AMD64 cores supported by CentOS 4? The RedHat page https://www.redhat.com/software/rhel/configuration/ suggests that RHEL 4 AS supports up to 8 AMD64/EM64T logical cpus. Is that accurate and does it apply to CentOS 4? I see a few vendors offering boxes with 8 (dual core) CPU sockets. IWILL for one. Thanks, Tony Schreiner Boston College