Displaying 3 results from an estimated 3 matches for "createpostmachineschedul".
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createpostmachinescheduler
2017 Feb 10
3
Enforcing in post-RA scheduling to keep (two) MachineInstrs together
Hello.
I am using the post-RA (Register Allocation) scheduler to avoid data hazards by
inserting other USEFUL instructions from the program (besides NOPs) and it breaks apart
some sequences of instructions which should remain "glued" together.
More exactly, in my [Target]ISelDAGToDAG.cpp it is possible that I replace for
example a BUILD_VECTOR with a machine SDNode called
2016 Oct 12
3
Dragon egg not recognizing Target ARM machine
...odeGen/Passes.h:216:
3: warning: unused parameter ‘C’ [-Wunused-parameter]
createMachineScheduler(MachineSchedContext *C) const {
^
/gaia/class/student/seerangv/LLVM_DIR/install/include/llvm/CodeGen/Passes.h:223:
3: warning: unused parameter ‘C’ [-Wunused-parameter]
createPostMachineScheduler(MachineSchedContext *C) const {
^
In file included from
/gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp:28:0:
/gaia/class/student/seerangv/DRAGONEGG_DIR/src/Backend.cpp: In function
‘void CreateTargetMachine(const string&)’:
/gaia/class/student/seerangv/DRAGONEGG_DIR/include/arm...
2020 Jul 11
2
[RFC] Introducing classes for the codegen driven by new pass manager
...atures already. This makes `class CodeGenPassBuilder` only do what it is supposed to do. PassInstrumentation is also more flexible than inserting debugging passes into the pipeline.
`class TargetPassConfig`(3) is partially ported to TargetMachine::options. The rest, such as `createMachineScheduler/createPostMachineScheduler`, are left out for now. They should be implemented in LLVMTargetMachine in the future.
Since the machine pass manager runs standalone and codegen process includes both IR pipeline(codegen prepare, EH, etc.) and MIR pipeline, the new codegen pipeline uses a pair of module pass manager and machine...