Displaying 2 results from an estimated 2 matches for "cpuregsregisterclass".
2012 Oct 26
1
[LLVMdev] Properly handling mem-loc arguments when prologue adjusts FP.
...trConstant(VA.getLocMemOffset()));
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo(),false, false, 0));
}
...
[2]: LowerFormalArguments
...
if (VA.isRegLoc()) {
// Arguments passed in registers.
const TargetRegisterClass *RC = ARC::CPURegsRegisterClass;
unsigned int Register = MF.addLiveIn(VA.getLocReg(), RC);
EVT RegisterValueType = VA.getLocVT();
ArgValue = DAG.getCopyFromReg(Chain, dl, Register, RegisterValueType);
InVals.push_back(ArgValue);
} else {
// Sanity check
assert(VA.isMemLoc());
// Loa...
2012 Jan 26
1
[LLVMdev] getMinimalPhysRegClass
Does anyone understand the purpose of this target inpdendent function?
By adding a new register class that is for MIPS16 but not even
referencing it, the compiler breaks because of this code.
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
V0, V1, A0, A1, A2, A3,
// Callee save
S0, S1
)>;
I'm trying to understand how the