Displaying 20 results from an estimated 142 matches for "cpufeature".
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2016 Mar 29
1
[PATCH 02/10] x86/cpufeature: Kill cpu_has_hypervisor
...Use boot_cpu_has() instead.
Signed-off-by: Borislav Petkov <bp at suse.de>
Cc: virtualization at lists.linux-foundation.org
Cc: sparmaintainer at unisys.com
---
arch/x86/events/intel/cstate.c | 2 +-
arch/x86/events/intel/uncore.c | 2 +-
arch/x86/include/asm/cpufeature.h | 1 -
arch/x86/kernel/cpu/vmware.c | 2 +-
arch/x86/kernel/kvm.c | 2 +-
drivers/staging/unisys/visorbus/visorchipset.c | 2 +-
6 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/...
2016 Mar 29
1
[PATCH 02/10] x86/cpufeature: Kill cpu_has_hypervisor
...Use boot_cpu_has() instead.
Signed-off-by: Borislav Petkov <bp at suse.de>
Cc: virtualization at lists.linux-foundation.org
Cc: sparmaintainer at unisys.com
---
arch/x86/events/intel/cstate.c | 2 +-
arch/x86/events/intel/uncore.c | 2 +-
arch/x86/include/asm/cpufeature.h | 1 -
arch/x86/kernel/cpu/vmware.c | 2 +-
arch/x86/kernel/kvm.c | 2 +-
drivers/staging/unisys/visorbus/visorchipset.c | 2 +-
6 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/...
2020 Feb 11
0
[PATCH 03/62] x86/cpufeatures: Add SEV-ES CPU feature
...ted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/amd.c | 4 +++-
arch/x86/kernel/cpu/scattered.c | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index f3327cb56edf..26e4ee209f7b 100644
--- a/arch/x86/include/asm/c...
2020 Apr 28
0
[PATCH v3 04/75] x86/cpufeatures: Add SEV-ES CPU feature
...ted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.
Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
Signed-off-by: Joerg Roedel <jroedel at suse.de>
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/amd.c | 3 ++-
arch/x86/kernel/cpu/scattered.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index db189945e9b0..ade59fca283a 100644
--- a/arch/x86/include/asm/cp...
2011 May 30
6
[PATCH] CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7
CPUID level 0x00000007:0 (ebx) is word 9, instead of word 7.
... make it consistent with native Linux.
Signed-off-by: Li Xin <xin.li@intel.com>
diff -r d7c755c25bb9 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Sat May 28 08:58:08 2011 +0100
+++ b/xen/include/asm-x86/cpufeature.h Tue May 31 07:34:34 2011 +0800
@@ -142,7 +142,7 @@
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
/* Intel-defined CPU features, CPUID level 0x0000000...
2015 Nov 18
4
[PATCH 1/3] x86/xen: Avoid fast syscall path for Xen PV guests
..._XENPV
> jz .Lsyscall_32_done
Could we make this a little less subtle:
ALTERNATIVE "testl %eax, %eax; lz .Lsyscall_32_done", "jmp
.Lsyscasll_32_done", X86_FEATURE_XENPV
Borislav, what do you think?
Ditto for the others.
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index e4f8010..0e4fe5b 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -216,6 +216,7 @@
> #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */
> #define X86_FEATURE_P...
2015 Nov 18
4
[PATCH 1/3] x86/xen: Avoid fast syscall path for Xen PV guests
..._XENPV
> jz .Lsyscall_32_done
Could we make this a little less subtle:
ALTERNATIVE "testl %eax, %eax; lz .Lsyscall_32_done", "jmp
.Lsyscasll_32_done", X86_FEATURE_XENPV
Borislav, what do you think?
Ditto for the others.
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index e4f8010..0e4fe5b 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -216,6 +216,7 @@
> #define X86_FEATURE_PAUSEFILTER ( 8*32+13) /* AMD filtered pause intercept */
> #define X86_FEATURE_P...
2015 Nov 18
0
[PATCH 1/3] x86/xen: Avoid fast syscall path for Xen PV guests
...usergs_sysret32 paravirt op (in
the subsequent patch)
Signed-off-by: Boris Ostrovsky <boris.ostrovsky at oracle.com>
Suggested-by: Andy Lutomirski <luto at amacapital.net>
---
arch/x86/entry/entry_32.S | 3 ++-
arch/x86/entry/entry_64_compat.S | 6 ++++--
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/xen/enlighten.c | 4 +++-
4 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/x86/entry/entry_32.S b/arch/x86/entry/entry_32.S
index 3eb572e..901f186 100644
--- a/arch/x86/entry/entry_32.S
+++ b/arch/x86/entry/entry_32.S
@@ -308,7 +308,8 @@ sysenter_past_...
2013 Dec 02
0
[PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle
...Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
xen/arch/x86/hvm/hvm.c | 6 ++++++
xen/arch/x86/hvm/vmx/vmcs.c | 8 ++++++--
xen/include/asm-x86/cpufeature.h | 2 ++
xen/include/asm-x86/hvm/vmx/vmcs.h | 2 ++
xen/include/asm-x86/msr-index.h | 2 ++
5 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 9c88c73..0f7178b 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hv...
2008 May 06
4
[PATCH] fixup 3dnow! support
...bits. But this will
break kvm in cpus that don't have those instructions (which includes
my laptop). So we fixup our cpuid before exposing it to the guest.
Signed-off-by: Glauber Costa <gcosta at redhat.com>
---
arch/x86/kvm/x86.c | 22 ++++++++++++++++++----
include/asm-x86/cpufeature.h | 2 ++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 979f983..e79fcd5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -919,7 +919,7 @@ static int is_efer_nx(void)
return efer & EFER_NX;
}
-static void cpuid_f...
2008 May 06
4
[PATCH] fixup 3dnow! support
...bits. But this will
break kvm in cpus that don't have those instructions (which includes
my laptop). So we fixup our cpuid before exposing it to the guest.
Signed-off-by: Glauber Costa <gcosta at redhat.com>
---
arch/x86/kvm/x86.c | 22 ++++++++++++++++++----
include/asm-x86/cpufeature.h | 2 ++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 979f983..e79fcd5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -919,7 +919,7 @@ static int is_efer_nx(void)
return efer & EFER_NX;
}
-static void cpuid_f...
2015 Nov 18
8
[PATCH 0/3] Fix and cleanup for 32-bit PV sysexit
...(3):
x86/xen: Avoid fast syscall path for Xen PV guests
x86: irq_enable_sysexit pv op is no longer needed
x86: usergs_sysret32 pv op is no longer needed
arch/x86/entry/entry_32.S | 11 ++++-------
arch/x86/entry/entry_64_compat.S | 16 ++++++----------
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/include/asm/paravirt.h | 12 ------------
arch/x86/include/asm/paravirt_types.h | 17 -----------------
arch/x86/kernel/asm-offsets.c | 3 ---
arch/x86/kernel/asm-offsets_64.c | 1 -
arch/x86/kernel/paravirt.c | 12 ------------
arch/x86/kernel...
2015 Nov 18
8
[PATCH 0/3] Fix and cleanup for 32-bit PV sysexit
...(3):
x86/xen: Avoid fast syscall path for Xen PV guests
x86: irq_enable_sysexit pv op is no longer needed
x86: usergs_sysret32 pv op is no longer needed
arch/x86/entry/entry_32.S | 11 ++++-------
arch/x86/entry/entry_64_compat.S | 16 ++++++----------
arch/x86/include/asm/cpufeature.h | 1 +
arch/x86/include/asm/paravirt.h | 12 ------------
arch/x86/include/asm/paravirt_types.h | 17 -----------------
arch/x86/kernel/asm-offsets.c | 3 ---
arch/x86/kernel/asm-offsets_64.c | 1 -
arch/x86/kernel/paravirt.c | 12 ------------
arch/x86/kernel...
2007 Feb 01
0
[PATCH] hide RDTSCP feature flag from PV guests
...}
+ else if ( regs->eax == 0x80000001 )
+ {
+ /* Modify Feature Information. */
+ clear_bit(X86_FEATURE_RDTSCP % 32, &d);
+ }
else
{
(void)cpuid_hypervisor_leaves(regs->eax, &a, &b, &c, &d);
Index: 2007-01-16/xen/include/asm-x86/cpufeature.h
===================================================================
--- 2007-01-16.orig/xen/include/asm-x86/cpufeature.h 2006-04-24 15:28:58.000000000 +0200
+++ 2007-01-16/xen/include/asm-x86/cpufeature.h 2007-02-01 17:25:15.000000000 +0100
@@ -49,6 +49,7 @@
#define X86_FEATURE_MP (1*32+19) /*...
2008 Nov 19
0
[PATCH] support CPUID hypervisor feature bit
...TPR % 32, &c);
__clear_bit(X86_FEATURE_PDCM % 32, &c);
__clear_bit(X86_FEATURE_DCA % 32, &c);
+ __set_bit(X86_FEATURE_HYPERVISOR % 32, &c);
break;
case 0x80000001:
/* Modify Feature Information. */
Index: 2008-10-27/xen/include/asm-x86/cpufeature.h
===================================================================
--- 2008-10-27.orig/xen/include/asm-x86/cpufeature.h 2008-05-07 12:21:37.000000000 +0200
+++ 2008-10-27/xen/include/asm-x86/cpufeature.h 2008-11-19 10:15:13.000000000 +0100
@@ -94,6 +94,7 @@
#define X86_FEATURE_SSE4_2 (4*32+20)...
2018 Dec 13
2
[PATCH] kbuild, x86: revert macros in extended asm workarounds
Revert the following commits:
- 5bdcd510c2ac9efaf55c4cbd8d46421d8e2320cd
("x86/jump-labels: Macrofy inline assembly code to work around GCC inlining bugs")
- d5a581d84ae6b8a4a740464b80d8d9cf1e7947b2
("x86/cpufeature: Macrofy inline assembly code to work around GCC inlining bugs")
- 0474d5d9d2f7f3b11262f7bf87d0e7314ead9200.
("x86/extable: Macrofy inline assembly code to work around GCC inlining bugs")
- 494b5168f2de009eb80f198f668da374295098dd.
("x86/paravirt: Work around GCC inlining...
2018 Dec 13
2
[PATCH] kbuild, x86: revert macros in extended asm workarounds
Revert the following commits:
- 5bdcd510c2ac9efaf55c4cbd8d46421d8e2320cd
("x86/jump-labels: Macrofy inline assembly code to work around GCC inlining bugs")
- d5a581d84ae6b8a4a740464b80d8d9cf1e7947b2
("x86/cpufeature: Macrofy inline assembly code to work around GCC inlining bugs")
- 0474d5d9d2f7f3b11262f7bf87d0e7314ead9200.
("x86/extable: Macrofy inline assembly code to work around GCC inlining bugs")
- 494b5168f2de009eb80f198f668da374295098dd.
("x86/paravirt: Work around GCC inlining...
2017 Oct 04
1
[PATCH 11/13] x86/paravirt: Add paravirt alternatives infrastructure
...tting rid of .parainstructions and pv
ops completely.
Suggested-by: Andy Lutomirski <luto at kernel.org>
Signed-off-by: Josh Poimboeuf <jpoimboe at redhat.com>
---
arch/x86/include/asm/alternative-asm.h | 9 +++-
arch/x86/include/asm/alternative.h | 12 +++--
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/paravirt-asm.h | 10 ++++
arch/x86/include/asm/paravirt_types.h | 84 ++++++++++++++++++++++++++++++++++
arch/x86/kernel/alternative.c | 13 ++++++
arch/x86/kernel/cpu/hypervisor.c | 2 +
arch/x86/kernel/module.c | 11 ++++-
arch...
2006 Aug 28
2
Extending dmitest to check for Long Mode (aka 64 versus 32 bit)
...fortunately, my understanding of what EDX and EAX means is zero... but
looking through your code I suspect that this may be the missing entry from
the cpu_flags_strings table in dmi_processor.h:
NULL, /* 30 */
In the Linux kernel I see that /proc/cpuinfo is determined through the
/usr/include/asm/cpufeature.h include as:
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
Would I simply need to Change the NULL entry to a string in
cpu_flags_strings table, add a bool in s_cpu_flags and then
dmi.c would automagically set the boolean correctly ?
I could then modify dmitest to check for...
2018 Oct 07
0
PROPOSAL: Extend inline asm syntax with size spec
...problematic arises when one ends up using a lot of inline
asm statements in the kernel but due to the inline asm cost estimation
heuristic which counts lines, I think, for example like in this here
macro:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/cpufeature.h#n162
the resulting code ends up not inlining the functions themselves which
use this macro. I.e., you see a CALL <function> instead of its body
getting inlined directly.
Even though it should be because the actual instructions are only a
couple in most cases and all those other directives...