Displaying 3 results from an estimated 3 matches for "cpu_prep".
2013 Aug 28
2
[PATCH 3/6] drm/nouveau: hook up cache sync functions
...wait_gpu);
> if (ret)
> diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
> index 830cb7b..f632b92 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_gem.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
> @@ -901,6 +901,11 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
> ret = ttm_bo_wait(&nvbo->bo, true, true, no_wait);
> spin_unlock(&nvbo->bo.bdev->fence_lock);
> drm_gem_object_unreference_unlocked(gem);
> +
> + if (!ret && nvbo->bo.ttm && nvbo->bo.ttm->caching_st...
2013 Aug 28
0
[PATCH 3/6] drm/nouveau: hook up cache sync functions
...)
> > diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
> > index 830cb7b..f632b92 100644
> > --- a/drivers/gpu/drm/nouveau/nouveau_gem.c
> > +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
> > @@ -901,6 +901,11 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data,
> > ret = ttm_bo_wait(&nvbo->bo, true, true, no_wait);
> > spin_unlock(&nvbo->bo.bdev->fence_lock);
> > drm_gem_object_unreference_unlocked(gem);
> > +
> > + if (!ret && nvbo->bo.ttm && nvbo-...
2015 Feb 26
2
[PATCH] gem: allow user-space to specify an object should be coherent
User-space use mappable BOs notably for fences, and expects that a
value update by the GPU will be immediatly visible through the
user-space mapping.
ARM has a property that may prevent this from happening though: memory
can be mapped multiple times only if the different mappings share the
same caching properties. However all the lowmem memory is already
identity-mapped into the kernel with cache