search for: cpu_mode_ssefp

...ones in our initial patch: #define CPU_MODE_NONE 0 #define CPU_MODE_MMX 1 // Base Intel MMX x86 #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions #define CPU_MODE_SSE 4 // Intel Integer SSE instructions #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers #define CPU_MODE_SSE2 32 // Intel SSE2 instructions #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. Potential Additions include some of the ASM modes. With the results that we found there is a relationship that looks like this: 3D...

...> #define CPU_MODE_NONE 0 > #define CPU_MODE_MMX 1 // Base Intel MMX x86 > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. You may wish to save space for PNI. http://cedar.intel.com/media/pdf/PNI_LEGAL3.pdf Likewise, all that branching...

...> #define CPU_MODE_NONE 0 > #define CPU_MODE_MMX 1 // Base Intel MMX x86 > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. If you reall want to define stuff like that, you could have simply NONE MMX 3DNOW 3DNOWEXT SSE1 SSE2 ALTIVEC Even then, M...

...E 0 > > #define CPU_MODE_MMX 1 // Base Intel MMX x86 > > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers > > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions > > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. > >If you reall want to define stuff like that, you could have simply >NONE >MMX >3DNOW >3DNOWE...

Jean-Marc, >I'm still not sure I get it. On an Athlon XP, I can do something like >"mulps xmm0, xmm1", which means that the xmm registers are indeed >supported. Besides, without the xmm registers, you can't use much of >SSE. In the Atholon XP 2400+ that we have in our QA lab (Win2000 ) if you run that code it generates an Illegal Instruction Error. In addition,