search for: cpu_mode_sse2

...MX 1 // Base Intel MMX x86 #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions #define CPU_MODE_SSE 4 // Intel Integer SSE instructions #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers #define CPU_MODE_SSE2 32 // Intel SSE2 instructions #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. Potential Additions include some of the ASM modes. With the results that we found there is a relationship that looks like this: 3DNOW implies MMX. 3DNOWEXT implies SSE. SSE2 implies SSEFP. SSEFP implies S...

...MMX x86 > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. You may wish to save space for PNI. http://cedar.intel.com/media/pdf/PNI_LEGAL3.pdf Likewise, all that branching is probably going to cause more trouble than it saves. Try this: vect...

...MMX x86 > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. If you reall want to define stuff like that, you could have simply NONE MMX 3DNOW 3DNOWEXT SSE1 SSE2 ALTIVEC Even then, MMX is completely useless for Speex IMO and I doubt it's worth writing 3DNow...

...e CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers > > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions > > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support. > >If you reall want to define stuff like that, you could have simply >NONE >MMX >3DNOW >3DNOWEXT >SSE1 >SSE2 >ALTIVEC > >Even then, MMX is completely useless for Sp...

Jean-Marc, >I'm still not sure I get it. On an Athlon XP, I can do something like >"mulps xmm0, xmm1", which means that the xmm registers are indeed >supported. Besides, without the xmm registers, you can't use much of >SSE. In the Atholon XP 2400+ that we have in our QA lab (Win2000 ) if you run that code it generates an Illegal Instruction Error. In addition,