Displaying 5 results from an estimated 5 matches for "cpu_mode_ss".
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cpu_mode_sse
2004 Aug 06
6
[PATCH] Make SSE Run Time option.
...be settable with a non FP SSE mode so that exceptions are avoided.
I thus propose a set of defines like this instead of the ones in our
initial patch:
#define CPU_MODE_NONE 0
#define CPU_MODE_MMX 1 // Base Intel MMX x86
#define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions
#define CPU_MODE_SSE 4 // Intel Integer SSE instructions
#define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
#define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
#define CPU_MODE_SSE2 32 // Intel SSE2 instructions
#define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support.
Pote...
2004 Aug 06
0
[PATCH] Make SSE Run Time option.
...o that exceptions are avoided.
>
> I thus propose a set of defines like this instead of the ones in our
> initial patch:
>
> #define CPU_MODE_NONE 0
> #define CPU_MODE_MMX 1 // Base Intel MMX x86
> #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions
> #define CPU_MODE_SSE 4 // Intel Integer SSE instructions
> #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
> #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
> #define CPU_MODE_SSE2 32 // Intel SSE2 instructions
> #define CPU_MODE_ALTIVEC 64 // PowerPC Al...
2004 Aug 06
0
[PATCH] Make SSE Run Time option.
...are part of the extended 3DNow!.
> I thus propose a set of defines like this instead of the ones in our
> initial patch:
>
> #define CPU_MODE_NONE 0
> #define CPU_MODE_MMX 1 // Base Intel MMX x86
> #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions
> #define CPU_MODE_SSE 4 // Intel Integer SSE instructions
> #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
> #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
> #define CPU_MODE_SSE2 32 // Intel SSE2 instructions
> #define CPU_MODE_ALTIVEC 64 // PowerPC Al...
2004 Aug 06
2
[PATCH] Make SSE Run Time option.
...> > I thus propose a set of defines like this instead of the ones in our
> > initial patch:
> >
> > #define CPU_MODE_NONE 0
> > #define CPU_MODE_MMX 1 // Base Intel MMX x86
> > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions
> > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions
> > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
> > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
> > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions
> > #define CPU_MODE_ALTIV...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
Jean-Marc,
>I'm still not sure I get it. On an Athlon XP, I can do something like
>"mulps xmm0, xmm1", which means that the xmm registers are indeed
>supported. Besides, without the xmm registers, you can't use much of
>SSE.
In the Atholon XP 2400+ that we have in our QA lab (Win2000 ) if you run
that code it generates an Illegal Instruction Error. In addition,