search for: cpu_mode_none

...s that Windows 2000 and below does not support them. We agree on not supporting the non-FP version, however the run time flags need to be settable with a non FP SSE mode so that exceptions are avoided. I thus propose a set of defines like this instead of the ones in our initial patch: #define CPU_MODE_NONE 0 #define CPU_MODE_MMX 1 // Base Intel MMX x86 #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions #define CPU_MODE_SSE 4 // Intel Integer SSE instructions #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support f...

...> support them. > > We agree on not supporting the non-FP version, however the run time flags > need to be settable with a non FP SSE mode so that exceptions are avoided. > > I thus propose a set of defines like this instead of the ones in our > initial patch: > > #define CPU_MODE_NONE 0 > #define CPU_MODE_MMX 1 // Base Intel MMX x86 > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > #define CPU_MODE_SSEFP 16 // SSE F...

...es using xmm registers). What AMD calls SSE is not SSE at all. Basically, it's a bunch of "extra instructions" borrowed from SSE and that are part of the extended 3DNow!. > I thus propose a set of defines like this instead of the ones in our > initial patch: > > #define CPU_MODE_NONE 0 > #define CPU_MODE_MMX 1 // Base Intel MMX x86 > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > #define CPU_MODE_SSEFP 16 // SSE F...

...AMD calls SSE is not SSE at all. >Basically, it's a bunch of "extra instructions" borrowed from SSE and >that are part of the extended 3DNow!. > > > I thus propose a set of defines like this instead of the ones in our > > initial patch: > > > > #define CPU_MODE_NONE 0 > > #define CPU_MODE_MMX 1 // Base Intel MMX x86 > > #define CPU_MODE_3DNOW 2 // Base AMD 3Dnow extensions > > #define CPU_MODE_SSE 4 // Intel Integer SSE instructions > > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions > > #define C...

Jean-Marc, >I'm still not sure I get it. On an Athlon XP, I can do something like >"mulps xmm0, xmm1", which means that the xmm registers are indeed >supported. Besides, without the xmm registers, you can't use much of >SSE. In the Atholon XP 2400+ that we have in our QA lab (Win2000 ) if you run that code it generates an Illegal Instruction Error. In addition,