Displaying 5 results from an estimated 5 matches for "cpu_mode_altivec".
2004 Aug 06
6
[PATCH] Make SSE Run Time option.
...2 // Base AMD 3Dnow extensions
#define CPU_MODE_SSE 4 // Intel Integer SSE instructions
#define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
#define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
#define CPU_MODE_SSE2 32 // Intel SSE2 instructions
#define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support.
Potential Additions include some of the ASM modes.
With the results that we found there is a relationship that looks like this:
3DNOW implies MMX. 3DNOWEXT implies SSE. SSE2 implies SSEFP. SSEFP implies
SSE. Either way, all the current Speex SSE should be flag ch...
2004 Aug 06
0
[PATCH] Make SSE Run Time option.
...xtensions
> #define CPU_MODE_SSE 4 // Intel Integer SSE instructions
> #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
> #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
> #define CPU_MODE_SSE2 32 // Intel SSE2 instructions
> #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support.
You may wish to save space for PNI.
http://cedar.intel.com/media/pdf/PNI_LEGAL3.pdf
Likewise, all that branching is probably going to cause more trouble than
it saves. Try this:
vector float a0 = vec_ld( 0, a );
vector float a1 = vec_ld(...
2004 Aug 06
0
[PATCH] Make SSE Run Time option.
...xtensions
> #define CPU_MODE_SSE 4 // Intel Integer SSE instructions
> #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
> #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
> #define CPU_MODE_SSE2 32 // Intel SSE2 instructions
> #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support.
If you reall want to define stuff like that, you could have simply
NONE
MMX
3DNOW
3DNOWEXT
SSE1
SSE2
ALTIVEC
Even then, MMX is completely useless for Speex IMO and I doubt it's
worth writing 3DNow non-ext code (or even 3DNow! at all). Same for SSE2:
Speex simpl...
2004 Aug 06
2
[PATCH] Make SSE Run Time option. Add Win32 SSE code
Jean-Marc,
>I'm still not sure I get it. On an Athlon XP, I can do something like
>"mulps xmm0, xmm1", which means that the xmm registers are indeed
>supported. Besides, without the xmm registers, you can't use much of
>SSE.
In the Atholon XP 2400+ that we have in our QA lab (Win2000 ) if you run
that code it generates an Illegal Instruction Error. In addition,
2004 Aug 06
2
[PATCH] Make SSE Run Time option.
...ne CPU_MODE_SSE 4 // Intel Integer SSE instructions
> > #define CPU_MODE_3DNOWEXT 8 // AMD 3Dnow extended instructions
> > #define CPU_MODE_SSEFP 16 // SSE FP modes, mainly support for xmm registers
> > #define CPU_MODE_SSE2 32 // Intel SSE2 instructions
> > #define CPU_MODE_ALTIVEC 64 // PowerPC Altivec support.
>
>If you reall want to define stuff like that, you could have simply
>NONE
>MMX
>3DNOW
>3DNOWEXT
>SSE1
>SSE2
>ALTIVEC
>
>Even then, MMX is completely useless for Speex IMO and I doubt it's
>worth writing 3DNow non-ext code (or...