search for: cpu_has_vmx_virtual_intr_delivery

.../ - pt_update_irq(v); + pt_vector = pt_update_irq(v); do { intack = hvm_vcpu_has_pending_irq(v); @@ -227,16 +228,34 @@ void vmx_intr_assist(void) goto out; intblk = hvm_interrupt_blocked(v, intack); - if ( intblk == hvm_intblk_tpr ) + if ( cpu_has_vmx_virtual_intr_delivery ) + { + /* Set "Interrupt-window exiting" for ExtINT */ + if ( (intblk != hvm_intblk_none) && + ( (intack.source == hvm_intsrc_pic) || + ( intack.source == hvm_intsrc_vector) ) ) + { + enable_in...

...A32_CR_PAT, MSR_TYPE_R | MSR_TYPE_W); - if ( cpu_has_vmx_apic_reg_virt ) - { - int msr; - for (msr = MSR_IA32_APICBASE_MSR; msr <= MSR_IA32_APICBASE_MSR + 0xff; msr++) - vmx_disable_intercept_for_msr(v, msr, MSR_TYPE_R); - } - if ( cpu_has_vmx_virtual_intr_delivery ) - { - vmx_disable_intercept_for_msr(v, MSR_IA32_APICTPR_MSR, MSR_TYPE_W); - vmx_disable_intercept_for_msr(v, MSR_IA32_APICEOI_MSR, MSR_TYPE_W); - vmx_disable_intercept_for_msr(v, MSR_IA32_APICSELF_MSR, MSR_TYPE_W); - } } /* I/O access bit...

...if (v->arch.hvm_vmx.eoi_exitmap_changed) { diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 4d7c93f..43ed36c 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1419,6 +1419,28 @@ static int vmx_virtual_intr_delivery_enabled(void) return cpu_has_vmx_virtual_intr_delivery; } +static void vmx_process_isr(int isr, struct vcpu *v) +{ + unsigned long status; + u8 old; + + if ( !cpu_has_vmx_virtual_intr_delivery ) + return; + + if (isr < 0) + isr = 0; + + vmx_vmcs_enter(v); + status = __vmread(GUEST_INTR_STATUS); + old = status &g...

...++-- 2 files changed, 44 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/intr.c b/xen/arch/x86/hvm/vmx/intr.c index 535248a..c5c503e 100644 --- a/xen/arch/x86/hvm/vmx/intr.c +++ b/xen/arch/x86/hvm/vmx/intr.c @@ -324,7 +324,9 @@ void vmx_intr_assist(void) } out: - if ( !cpu_has_vmx_virtual_intr_delivery && cpu_has_vmx_tpr_shadow ) + if ( !nestedhvm_vcpu_in_guestmode(v) && + !cpu_has_vmx_virtual_intr_delivery && + cpu_has_vmx_tpr_shadow ) __vmwrite(TPR_THRESHOLD, tpr_threshold); } diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/...

...t_guestmode(v); nvcpu->nv_vmexit_pending = 0; + nvcpu->nv_vmswitch_in_progress = 1; lm_l2 = !!hvm_long_mode_enabled(v); lm_l1 = !!(__get_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_CONTROLS) & @@ -1371,6 +1372,7 @@ static void virtual_vmexit(struct cpu_user_regs *regs) if ( cpu_has_vmx_virtual_intr_delivery ) nvmx_update_apicv(v); + nvcpu->nv_vmswitch_in_progress = 0; vmreturn(regs, VMSUCCEED); } @@ -1876,6 +1878,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content) data = SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING | SECONDARY_EXEC_VIRTUALI...

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

From: Yang Zhang <yang.z.zhang@Intel.com> The follwoing patches are adding the Posted Interrupt supporting to Xen: Posted Interrupt allows vAPIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu. Then the vcpu will handle this