search for: cpu_has

...26d..d88866c 100644 --- a/arch/x86/kernel/acpi/processor.c +++ b/arch/x86/kernel/acpi/processor.c @@ -60,7 +60,7 @@ static void init_intel_pdc(struct acpi_processor *pr, struct cpuinfo_x86 *c) /* * If mwait/monitor is unsupported, C2/C3_FFH will be disabled */ - if (!cpu_has(c, X86_FEATURE_MWAIT)) + if (!cpu_has(c, X86_FEATURE_MWAIT) && !xen_initial_domain()) buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); obj->type = ACPI_TYPE_BUFFER; Above trick is ugly and error-prone, since it always enable mwait regardless of actual CPU capability...

...o the emulator. Is that really correct (in particular in the context of real mode emulation, where it''s not just single instructions that get emulated)? >From earlier work on the emulation code I seem to recall that it''s mainly the testing code that didn''t like use of cpu_has_xyz in conditionals. I would suppose that simply adding respective feature detection (and boolean variables) to the testing code should get us around this problem. Or would you see any better alternative? Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists....

...arch/x86/hvm/vmx/vpmu_core2.c Tue Mar 12 13:58:40 2013 +0100 @@ -607,6 +607,10 @@ static void core2_vpmu_do_cpuid(unsigned { /* Switch on the ''Debug Store'' feature in CPUID.EAX[1]:EDX[21] */ *edx |= cpufeat_mask(X86_FEATURE_DS); + if ( cpu_has(&current_cpu_data, X86_FEATURE_DTES64) ) + *ecx |= cpufeat_mask(X86_FEATURE_DTES64); + if ( cpu_has(&current_cpu_data, X86_FEATURE_DSCPL) ) + *ecx |= cpufeat_mask(X86_FEATURE_DSCPL); } } } -- Company details: http://ts.fujitsu.com/i...

...XT (6*32+22) /* topology extensions CPUID leafs */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ -#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ +#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...t_cpu_flag_value_from_name(s_cpu *cpu, const char * flag); #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 -#define X86_VENDOR_UNKNOWN 9 -#define X86_VENDOR_NUM 10 +#define X86_VENDOR_HYGON 9 +#define X86_VENDOR_UNKNOWN 10 +#define X86_VENDOR_NUM 11 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) diff --git a/com32/gpllib/cpuid.c b/com32/gpllib/cpuid.c index 2abd0bda..0681dbce 100644 --- a/com32/gpllib/cpuid.c +++ b/com32/gpllib/cpuid.c @@ -60,6 +60,11 @@ static struct cpu_dev amd_cpu_dev = { .c_ident = {"AuthenticAMD&...

From: Borislav Petkov <bp at suse.de> Using static_cpu_has() is pointless on those paths, convert them to the boot_cpu_has() variant. No functional changes. Reported-by: Nadav Amit <nadav.amit at gmail.com> Signed-off-by: Borislav Petkov <bp at suse.de> Cc: Aubrey Li <aubrey.li at intel.com> Cc: Dave Hansen <dave.hansen at intel.com&...

...t_cpu_flag_value_from_name(s_cpu *cpu, const char * flag); #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 #define X86_VENDOR_NSC 8 -#define X86_VENDOR_UNKNOWN 9 -#define X86_VENDOR_NUM 10 +#define X86_VENDOR_HYGON 9 +#define X86_VENDOR_UNKNOWN 10 +#define X86_VENDOR_NUM 11 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) diff --git a/com32/gpllib/cpuid.c b/com32/gpllib/cpuid.c index 2abd0bda..0681dbce 100644 --- a/com32/gpllib/cpuid.c +++ b/com32/gpllib/cpuid.c @@ -60,6 +60,11 @@ static struct cpu_dev amd_cpu_dev = { .c_ident = {"AuthenticAMD&...

..."rdtscp" : "=A" (dummy), "=c" (p)); } else { /* Load per CPU data from GDT */ asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG)); @@ -256,7 +257,11 @@ static void __cpuinit vsyscall_set_cpu(i node = cpu_to_node[cpu]; #endif if (cpu_has(&cpu_data[cpu], X86_FEATURE_RDTSCP)) - write_rdtscp_aux((node << 12) | cpu); + /* This is write_rdtscp_aux. It cannot be called directly + * due to the paravirt indirection */ + asm("wrmsr" : /* no output */ + : "d"(0), + "a" ((node <<...

...oot line via two methods: @@ -329,6 +370,24 @@ static void __devinit init_amd(struct cp 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ clear_bit(0*32+31, c->x86_capability); +#ifdef CONFIG_X86_64 + if (c->x86 == 0xf && c->x86_model < 0x14 + && cpu_has(c, X86_FEATURE_LAHF_LM)) { + /* + * Some BIOSes incorrectly force this feature, but only K8 + * revision D (model = 0x14) and later actually support it. + * (AMD Erratum #110, docId: 25759). + */ + unsigned int lo, hi; + + clear_bit(X86_FEATURE_LAHF_LM, c->x86_capability); + if (!rdm...

..."rdtscp" : "=A" (dummy), "=c" (p)); } else { /* Load per CPU data from GDT */ asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG)); @@ -256,7 +257,11 @@ static void __cpuinit vsyscall_set_cpu(i node = cpu_to_node[cpu]; #endif if (cpu_has(&cpu_data[cpu], X86_FEATURE_RDTSCP)) - write_rdtscp_aux((node << 12) | cpu); + /* This is write_rdtscp_aux. It cannot be called directly + * due to the paravirt indirection */ + asm("wrmsr" : /* no output */ + : "d"(0), + "a" ((node <<...

...2 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 9c88c73..0f7178b 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2905,6 +2905,12 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, if ( (count == 0) && !cpu_has_smep ) *ebx &= ~cpufeat_mask(X86_FEATURE_SMEP); + /* Don''t expose MPX to hvm when VMX support is not available */ + if ( (count == 0) && + (!(vmx_vmexit_control & VM_EXIT_CLEAR_BNDCFGS) || + !(vmx_vmentry_control & V...

...arch/x86/hvm/svm/svm.c 2007-08-08 11:43:53.000000000 +0200 @@ -68,6 +68,11 @@ static void *hsa[NR_CPUS] __read_mostly; /* vmcb used for extended host state */ static void *root_vmcb[NR_CPUS] __read_mostly; +#ifdef __x86_64__ +/* indicate whether guest may use EFER.LMSLE */ +static unsigned char cpu_has_lmsl = 1; +#endif + /* SVM feature flags */ u32 svm_feature_flags; @@ -190,7 +195,10 @@ static enum handler_return long_mode_do_ case MSR_EFER: /* Offending reserved bit will cause #GP. */ #ifdef __x86_64__ - if ( (msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_S...

...#define X86_FEATURE_BMI2 (7*32+ 8) /* 2nd bit manipulation extensions */ #define X86_FEATURE_ERMS (7*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */ +#define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel

Hi, This series corresponds do older patches in the paravirt series that was neither already applied, nor I will touch again. In general, they do not touch code that can be unified (at least, without being the unification a big problem on its own). They passed through this list a lot of times, so I feel them ready for inclusion, unless someone opposes. As with the other patches, they apply to

Hi, This series corresponds do older patches in the paravirt series that was neither already applied, nor I will touch again. In general, they do not touch code that can be unified (at least, without being the unification a big problem on its own). They passed through this list a lot of times, so I feel them ready for inclusion, unless someone opposes. As with the other patches, they apply to

...(6*32+ 7) /* Misaligned SSE Access */ +#define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */ +#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ +#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */ +#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

..."rdtscp" : "=A" (dummy), "=c" (p)); } else { /* Load per CPU data from GDT */ asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG)); @@ -257,7 +258,11 @@ static void __cpuinit vsyscall_set_cpu(i node = cpu_to_node[cpu]; #endif if (cpu_has(&cpu_data[cpu], X86_FEATURE_RDTSCP)) - write_rdtscp_aux((node << 12) | cpu); + /* This is write_rdtscp_aux. It cannot be called directly + * due to the paravirt indirection */ + asm("wrmsr" : /* no output */ + : "d"(0), + "a" ((node <<...

..."rdtscp" : "=A" (dummy), "=c" (p)); } else { /* Load per CPU data from GDT */ asm("lsl %1,%0" : "=r" (p) : "r" (__PER_CPU_SEG)); @@ -257,7 +258,11 @@ static void __cpuinit vsyscall_set_cpu(i node = cpu_to_node[cpu]; #endif if (cpu_has(&cpu_data[cpu], X86_FEATURE_RDTSCP)) - write_rdtscp_aux((node << 12) | cpu); + /* This is write_rdtscp_aux. It cannot be called directly + * due to the paravirt indirection */ + asm("wrmsr" : /* no output */ + : "d"(0), + "a" ((node <<...

Hello, The following patches are a solution to a problem we have encountered when using the Xen hypervisor: - Need Pxx/Cxx states to save on power consumption when using Xen (we do want those datacenters to consume less power!), - Also need to figure out the Turbo mode so that the scheduler can properly boost a core for CPU bound guests. In essence the Xen hypervisor requires that