search for: cpu74brcc_g

...that have a GR register as input. Both map to the same machine instructions through Pattern matching in TargetInstrInfo.td. This is what I mean, for the case of the Conditional Branch instruction : let Uses = [SR] in { def BRCC : T2ccbr< "br", "br"> ; } def : Pat<(CPU74brcc_g bb:$a, imm:$cc), (BRCC jmptarget:$a, imm:$cc, 0)>; def : Pat<(CPU74brcc_i bb:$a, imm:$cc, GR16:$ins), (BRCC jmptarget:$a, imm:$cc, GR16:$ins)>; Then, in MyTargetISelDAGToDAG I create ‘CPU74brcc_g' instructions if they are glued to a ‘compare’ instruction, or ‘CPU74brcc_i' instr...

Hi Eli, Thank you very much for your response. In fact, I had already tried the X86 approach before, i.e explicitly using the status register. This is the approach that appeals more to me. I left it parked because it also produced some problems (but I left it commented out). So I have now re-lived the code, and it works fine in most cases, but there’s a particular case that causes LLVM to stop