Displaying 3 results from an estimated 3 matches for "cpu74".
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2019 May 28
2
Instruction is selected, but it shouldn't (?)
In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register:
def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>;
def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>;
The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td:
class T5rr16alu<string opcStr...
2019 May 28
2
Instruction is selected, but it shouldn't (?)
...s, and the SP only has special instructions for it, I can NOT use the Thumb1 code implementation below:
SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
Chain = SP.getValue(1);
SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
I must use this instead:
SDValue SP = DAG.getRegister(CPU74::SP, VT);
SP = DAG.getNode(ISD::SUB, dl, MVT::i16, SP, Size);
The ‘getCopyFromReg’ code in the first excerpt produces suboptimal code because LLVM can not figure out a way to place the SP directly in the SUB instruction without using an intermediate register.
However, the code on the second exce...
2019 May 13
3
How to change CLang struct alignment behaviour?
Hi Joan,
On Mon, 13 May 2019 at 18:01, Joan Lluch <joan.lluch at icloud.com> wrote:
> After looking at it a bit further, I think this is a Clang thing. Clang issues “align 2” if the struct has at least one int (2 bytes), but also if the entire struct size is multiple of 2. For example a struct with 4 char members. In these cases the LLVM backend correctly creates word sized load/stores